US5894159A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor device having first and second insulating layers
Assignee: Sony Corp
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Filing: 1997-05-12
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Granted: 1999-04-13
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Expires: 2017-05-12
Abstract
Abstract A semiconductor device advantageously has first and second oxidized silicon insulating layers formed on the surface of a substrate. A first oxidized silicon insulating layer is formed through a low temperature process and a second oxidized silicon insulating layer may be formed at a higher manufacturing process temperature. Advantageously, the first oxidized silicon insulating layer has a lower voltage resistance than the second oxidized silicon insulating layer.
Inventors
- 👤 Hiroshi Mori
- 👤 Toshiyuki Sameshima
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 10:24
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/60; H10D64/66; H10D64/68; H10D64/681; H10D64/685; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227; H10D30/031; H10D30/0312; H10D30/0314; H10D30/0321; H10D30/60; H10D30/67; H10D30/6704; H10D30/6713; H10D30/6729; H10D30/6737; H10D30/6739; H10D64/01; H10D64/013; H10D64/01302; H10D64/01332; H10D64/01336; H10D64/01342; H10P; H10P14/00; H10P14/60; H10P14/63; H10P14/6326; H10P14/6328; H10P14/6332; H10P14/6334; H10P14/6336; H10P14/66; H10P14/662; H10D64/01346; H10P14/69; H10P14/692; H10P14/6921; H10P14/69215
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
72 words
A semiconductor device comprising: a first oxidized silicon layer; and a second oxidized silicon layer formed on the first oxidized silicon layer, wherein the second oxidized silicon layer has a higher voltage resistance than a voltage resistance of the first oxidized silicon layer, and wherein the voltage resistance of the first oxidized silicon layer is less than a voltage resistance of a silicon dioxide layer formed by thermal oxidation or thermal CVD.
Claim 2
Dependent Claim
72 words
A semiconductor device comprising: a first oxidized silicon layer; and a second oxidized silicon layer formed on the first oxidized silicon layer, wherein the second oxidized silicon layer has a higher voltage resistance than a voltage resistance of the first oxidized silicon layer, and wherein the voltage resistance of the first oxidized silicon layer is less than a voltage resistance of a silicon dioxide layer formed by thermal oxidation or thermal CVD.
Claim 3
Dependent Claim
25 words
A semiconductor device according to claim 1, wherein said first and second silicon dioxide layers are located between a substrate layer and a gate electrode.
Claim 4
Dependent Claim
15 words
A semiconductor device according to claim 2, wherein said substrate layer is a silicon layer.
Claim 5
Dependent Claim
33 words
A semiconductor device according to claim 2, wherein said substrate layer is placed adjacent to said first oxidized silicon layer, and said gate electrode is place adjacent to said second oxidized silicon layer.
Claim 6
Dependent Claim
13 words
The semiconductor device of claim 2, wherein the substrate is a glass substrate.
Claim 7
Dependent Claim
20 words
The semiconductor device of claim 1, wherein the first oxidized silicon layer has a thickness of less than 75 nm.
Claim 8
Dependent Claim
20 words
The semiconductor device of claim 2, wherein the first oxidized silicon layer has a thickness of less than 75 nm.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2002-04-12 | 2002-10-12 | 2003-04-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-04-12 | 2006-10-12 | 2007-04-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-04-12 | 2010-10-12 | 2011-04-13 | $7700.00 | Window Closed / Lapsed |