US5892287A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor device including stacked chips having metal patterned on circuit surface and on edge side of chip
Assignee: Texas Instruments Inc
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Filing: 1997-08-18
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Granted: 1999-04-06
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Expires: 2017-08-18
Abstract
Abstract A three-dimensional semiconductor circuit assembly wherein each of several circuit chips is provided with patterned metal layers that extend from the circuit surface onto an edge side of the chip, then the chips are adhesively bonded to opposite surfaces of one or more dielectric spacers, respectively, whereby the edge sides of the resulting multiple-chip stack are readily connected to metal patterns on a substrate.
Inventors
- 👤 Emily Ellen Hoffman
- 👤 Judith Sultenfuss Archer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 05:54
CPC Classifications
H; H10; H10W; H10W72/00; H10W72/20; H10P; H10P72/00; H10P72/70; H10P72/72; H10P72/722; H10W90/00; H10W70/00; H10W70/60; H10W70/62; H10W70/65; H10W72/071; H10W72/072; H10W72/07251; H10W72/07254; H10W72/241; H10W72/244; H10W72/247; H10W72/248; H10W72/251; H10W72/252; H10W72/834; H10W72/90; H10W72/921; H10W72/922; H10W72/923; H10W72/941; H10W72/944; H10W72/9445; H10W72/951; H10W72/952; H10W90/20; H10W90/231; H10W90/291; H10W90/701; H10W90/721; H10W90/723; H10W90/724
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
78 words
A three dimensional circuit assembly comprising: first and second circuit chips having a plurality of thin metal layers patterned on the circuit surface and extended onto an edge side of the chip; and a dielectric spacer having first and second adhesive films on opposite surfaces thereof respectively; said spacer having a first surface adhesively bonded to at least a portion of said first chip; the second adhesive surface of said spacer adhesively bonded to said second semiconductor chip.
Claim 2
Dependent Claim
78 words
A three dimensional circuit assembly comprising: first and second circuit chips having a plurality of thin metal layers patterned on the circuit surface and extended onto an edge side of the chip; and a dielectric spacer having first and second adhesive films on opposite surfaces thereof respectively; said spacer having a first surface adhesively bonded to at least a portion of said first chip; the second adhesive surface of said spacer adhesively bonded to said second semiconductor chip.
Claim 3
Dependent Claim
20 words
An assembly according to claim 1 wherein said dielectric spacer consists of a plastic core layer with two adhesive sides.
Claim 4
Dependent Claim
21 words
An assembly according to claim 1 wherein a plurality of solder bumps is positioned onto portions of said plurality of conductors.
Claim 5
Dependent Claim
27 words
An assembly according to claim 1 wherein the ends of said three-dimensional circuit assembly are electrically connected to a substrate having a plurality of conductive patters thereon.
Claim 6
Dependent Claim
16 words
An assembly according to claim 1 wherein said three-dimensional circuit assembly and said substrate are orthogonal.
Claim 7
Dependent Claim
100 words
A three-dimensional circuit assembly comprising: first and second semiconductor circuit chips having a plurality of thin metal layers patterned on the circuit surface and extended onto an edge side of the chip; a dielectric spacer having first and second adhesive films on opposite surfaces thereof respectively; said spacer having a first surface adhesively bonded to at least a portion of said first chip the second surface of said spacer adhesively bonded to said second semiconductor ship; and an interconnect substrate having a plurality of conducting patterns thereon electrically connected with the edge sides of said first and second semiconductor chips.
Claim 8
Dependent Claim
100 words
A three-dimensional circuit assembly comprising: first and second semiconductor circuit chips having a plurality of thin metal layers patterned on the circuit surface and extended onto an edge side of the chip; a dielectric spacer having first and second adhesive films on opposite surfaces thereof respectively; said spacer having a first surface adhesively bonded to at least a portion of said first chip the second surface of said spacer adhesively bonded to said second semiconductor ship; and an interconnect substrate having a plurality of conducting patterns thereon electrically connected with the edge sides of said first and second semiconductor chips.
Claim 9
Dependent Claim
17 words
An assembly according to claim 6 wherein first and second chips and said interconnect substrate are orthogonal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-04-05 | 2002-10-05 | 2003-04-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-04-05 | 2006-10-05 | 2007-04-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-04-05 | 2010-10-05 | 2011-04-06 | $7700.00 | Window Closed / Lapsed |