Method for manufacturing a semiconductor device having an adjustable channel width

Claim 1

A method of manufacturing a semiconductor device having a first transistor and a second transistor, the method comprising the steps of: forming a plurality of source and drain regions having a first conductivity type and substantially in parallel to each other on a surface of a semiconductor substrate, the semiconductor substrate having a second conductivity type that is opposite of the first conductivity type; forming a first channel region between a first pair of the plurality of source and drain regions and a second channel region between one of the first pair and a second pair of the plurality of source and drain regions; forming a gate insulating film on the semiconductor substrate; forming on the gate insulating film a plurality of gate electrodes that are substantially in parallel to each other and perpendicular to the plurality of source and drain regions; implanting ions into the first channel region by using one of the plurality of gate electrodes as a mask that substantially prevents the implantation of the ions, and by using a subsequent thermal diffusion process, to form an impurity diffusion region of the second conductivity type in the first channel region, thereby reducing the first channel region, wherein the impurity diffusion region has a second conductivity type concentration greater than that of the semiconductor substrate; wherein the reduced first channel region corresponds to the first transistor and the second channel region corresponds to the second transistor, and wherein a width of the reduced first channel region is less than a width of the second channel region.

Claim 2

A method of manufacturing a semiconductor device having a first transistor and a second transistor, the method comprising the steps of: forming a plurality of source and drain regions having a first conductivity type and substantially in parallel to each other on a surface of a semiconductor substrate, the semiconductor substrate having a second conductivity type that is opposite of the first conductivity type; forming a first channel region between a first pair of the plurality of source and drain regions and a second channel region between one of the first pair and a second pair of the plurality of source and drain regions; forming a gate insulating film on the semiconductor substrate; forming on the gate insulating film a plurality of gate electrodes that are substantially in parallel to each other and perpendicular to the plurality of source and drain regions; implanting ions into the first channel region by using one of the plurality of gate electrodes as a mask that substantially prevents the implantation of the ions, and by using a subsequent thermal diffusion process, to form an impurity diffusion region of the second conductivity type in the first channel region, thereby reducing the first channel region, wherein the impurity diffusion region has a second conductivity type concentration greater than that of the semiconductor substrate; wherein the reduced first channel region corresponds to the first transistor and the second channel region corresponds to the second transistor, and wherein a width of the reduced first channel region is less than a width of the second channel region.