EP0448141A1
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Programming process suitable for defining at least four different current levels in an ROM memory cell
Assignee: STMicroelectronics SRL
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Filing: 1991-02-20
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Granted: —
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Expires: 2011-02-20
Abstract
Abstract The programming process relates to an ROM memory cell which comprises a substrate of semiconductor material (4) including regions of source (1) and drain (2) and a channel region (6) over which a gate (5) is superimposed. Programming is carried out by ionic implantation using a mask (7) for covering said gate (5) having a width which can vary among at least four different dimensions.
Inventors
- 👤 Luigi Pascucci
- 👤 Marco Olivo
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-06 17:34
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/56; G11C11/5692; H; H10; H10B; H10B20/00
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
77 words
Programming process for an ROM memory cell constituted by a substrate of semiconductor material (4) including regions of source (1) and drain (2) and a channel region (6) between them, over which a gate (5) is superimposed, comprising the application of a mask (7) over said gate (5) and an implantation of dopant suitable for varying the cell's conductivity, characterized in that said mask (7) has a width which can vary among at least four different dimensions.
Claim 2
Dependent Claim
25 words
Process according to claim 1, characterised in that said mask (7) is superimposed centrally over gate (5) and essentially extends for 1/3 of its width.
Claim 3
Dependent Claim
25 words
Process according to claim 1, characterized in that said mask (7) is superimposed centrally over gate (5) and essentially extends for 2/3 of its width.
Claim 4
Dependent Claim
26 words
Process according to claim 1, characterised in that said mask covers said gate (5) entirely except for a central strip equal to 1/3 of its width.
Claim 5
Dependent Claim
26 words
Process according to claim 1, characterised in that said mask covers said gate (5) entirely except for a central strip equal to 2/3 of its width.
References Cited (Backward Citations)
EP0119729A1
Cited
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