Control circuit for a buffer memory to transfer data between systems operating at different speeds

Claim 2

A data transfer system configured to match data transfers from a first system with a first clock rate to a second system with a second clock rate, said data transfer system comprising: a data store including a plurality of memory locations, each memory location providing temporary storage for a data segment and configured to temporarily store data segments being transferred from said first system to said second system; an input terminal of said data store configured to accept data from said first system at said first clock rate; an output terminal of said data store configured to output data to said second system at said second clock rate; and a control circuit coupled to in parallel with said data store, said control circuit, including a plurality of memory cells including at least one flag memory cell, each memory cell corresponding to a memory location, each memory cell receiving a data unit when a corresponding memory location receives a data segment, the control circuit signaling when a threshold amount of data has been input into said data store.

Claim 3

The data transfer system of claim 1 wherein said plurality of memory cells is a shift register, and a unit of data is transferred from a first memory cell to a second memory cell in the plurality of memory cells in response to each input from said first system.

Claim 4

The data transfer system of claim 1 wherein said data store is a dual port RAM.

Claim 5

The data transfer system of claim 3 wherein said plurality of memory cells is a dual port RAM which successively loads memory cells according to an address given by an input counter.

Claim 6

The data transfer system of claim 1 wherein said control circuit includes a counter as a delay element.

Claim 7

The data transfer system of claim 1 wherein the number of memory cells in said plurality of memory cells is at least equal to a number of words in said data store.

Claim 8

The data transfer system of claim 1 wherein at least one flip-flop is coupled between the output of said plurality of memory cells and the input of said data store, said flip-flop running on said second clock rate.

Claim 9

The data transfer system of claim 1 wherein the output of said control circuit is coupled to a counter reset, said counter reset configured to reset a counter coupled to output address lines of said data store.

Claim 10

The data transfer system of claim 1 wherein said data transfer system is an asynchronous FIFO circuit.

Claim 13

The method of claim 10 wherein said ready signal is input into a reset input of a counter.

Claim 14

The method of claim 11, wherein said ready signal goes through at least one flip-flop clocked by said second clock before being input into the reset input of said counter.

Claim 15

The method of claim 11, wherein said counter is an output counter that identifies a memory address which hold s the data being output by said data transfer circuit.

Claim 16

The method of claim 10, wherein the generating of said ready signal based on said threshold value further comprises: timing additional inputs of additional bits of data into the plurality of memory cells; outputting the contents of one memory cell of said plurality of memory cells to a counter in said data transfer circuit.

Claim 17

An information processing system comprising: a first computing unit including a first processor and a first clock running at a first clock rate; a second computing unit including a second processor and a second clock running at a second clock rate; and a data transfer system configured to match data transfers from said first computing unit to said second computing unit, said data transfer system including: a data store including a plurality of memory locations, each memory location providing storage for a data word and configured to temporarily store the data word being transferred from said first computing unit to said second computing unit, an input terminal of said data store configured to accept the data word from said first computing unit at said first clock rate, an output terminal of said data store configured to output the data word to said second computing unit at said second clock rate, and a control circuit coupled to said data store, said control circuit including a plurality of memory cells including at least one flag memory cell, each memory cell corresponding to a memory location, each memory cell receiving a data unit when a corresponding memory location receives a word of data, the control circuit signaling when a threshold number of memory cells receives data unit.

Claim 18

An information processing system comprising: a first computing unit including a first processor and a first clock running at a first clock rate; a second computing unit including a second processor and a second clock running at a second clock rate; and a data transfer system configured to match data transfers from said first computing unit to said second computing unit, said data transfer system including: a data store including a plurality of memory locations, each memory location providing storage for a data word and configured to temporarily store the data word being transferred from said first computing unit to said second computing unit, an input terminal of said data store configured to accept the data word from said first computing unit at said first clock rate, an output terminal of said data store configured to output the data word to said second computing unit at said second clock rate, and a control circuit coupled to said data store, said control circuit including a plurality of memory cells including at least one flag memory cell, each memory cell corresponding to a memory location, each memory cell receiving a data unit when a corresponding memory location receives a word of data, the control circuit signaling when a threshold number of memory cells receives data unit.

Claim 19

The data transfer system of claim 1 wherein each memory cell in the plurality of memory cells corresponds to a memory unit in the data store for storing a word of data, each memory cell receiving a unit of data when a corresponding memory unit receives a word of data.

Claim 20

The data transfer system in claim 1 wherein the memory locations are nonconsecutive memory locations.

Claim 21

The data transfer system in claim 1 wherein the memory locations are consecutive memory locations.