US5592629A
Expired / Lapsed
US
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Apparatus and method for matching data rates to transfer data between two asynchronous devices
Assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Filing: 1992-12-28
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Granted: 1997-01-07
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Expires: 2012-12-28
Abstract
Abstract A method and apparatus for transferring data between two relatively asynchronous devices and yet matching the maximum data rate of each. Both an asynchronous FIFO and a synchronous FIFO are used to match the data rate of a high speed asynchronous device, such as a SCSI/SCSI2 controller, to a high speed synchronous device, such as a DMA controller. A high speed synchronizer controls both FIFOs such that the asynchronous and the synchronous devices can each run at its maximum data transfer rate during operation.
Inventors
- 👤 William H. Gamble
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 22:47
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/40; G06F13/4004; G06F13/4027; G06F13/405
Claims Analysis
Total Claims: 26
Claim 1
Independent Claim
166 words
A circuit for matching data rates to transfer data between two asynchronous devices, comprising: an asynchronous FIFO that has a first bi-directional data port, a second bi-directional data port, and a bi-directional control port; a synchronous FIFO, that has a first bi-directional data port, a second bi-directional data port, and a bi-directional control port, said first bi-directional data port of said synchronous FIFO connected to said second bi-directional data port of said asynchronous FIFO; and a synchronizer, that has a first bi-directional control port and a second bi-directional control port, said first bi-directional control port of said synchronizer connected to said bi-directional control port of said asynchronous FIFO and said second bi-directional control port connected to said bi-directional control port of said synchronous FIFO; wherein asynchronous data signals from one of said asynchronous devices are transferred between said first bi-directional data port of said asynchronous FIFO and said second bi-directional data port of said synchronous FIFO to the other of the asynchronous devices after a delay.
Claim 2
Dependent Claim
166 words
A circuit for matching data rates to transfer data between two asynchronous devices, comprising: an asynchronous FIFO that has a first bi-directional data port, a second bi-directional data port, and a bi-directional control port; a synchronous FIFO, that has a first bi-directional data port, a second bi-directional data port, and a bi-directional control port, said first bi-directional data port of said synchronous FIFO connected to said second bi-directional data port of said asynchronous FIFO; and a synchronizer, that has a first bi-directional control port and a second bi-directional control port, said first bi-directional control port of said synchronizer connected to said bi-directional control port of said asynchronous FIFO and said second bi-directional control port connected to said bi-directional control port of said synchronous FIFO; wherein asynchronous data signals from one of said asynchronous devices are transferred between said first bi-directional data port of said asynchronous FIFO and said second bi-directional data port of said synchronous FIFO to the other of the asynchronous devices after a delay.
Claim 3
Dependent Claim
21 words
A circuit, as set forth in claim 1, further comprising: means for controlling said asynchronous FIFO connected to said asynchronous FIFO.
Claim 4
Dependent Claim
21 words
A circuit, as set forth in claim 2, further comprising: means for controlling said synchronous FIFO connected to said synchronous FIFO.
Claim 5
Dependent Claim
32 words
A circuit, as set forth in claim 3, wherein said asynchronous FIFO is of a fall through type having three stages with each stage having a storage capacity of one data word.
Claim 6
Dependent Claim
21 words
A circuit, as set forth in claim 1, further comprising: means for controlling said synchronous FIFO connected to said synchronous FIFO.
Claim 7
Dependent Claim
133 words
A circuit for matching data rates to transfer data between two asynchronous devices, comprising: an asynchronous FIFO that has a data input, a data output, and a control output indicating that a data word is available for outputting; a synchronizer, that has a control input and a control output, said control input connected to said asynchronous FIFO control output; and a synchronous FIFO, that has a data input, a control input and a data output, said synchronous FIFO control input connected to said synchronizer control output and said data input connected to said asynchronous FIFO data output; wherein asynchronous data signals inputted on said asynchronous FIFO data input from one of the asynchronous devices are outputted to the other of the asynchronous devices at said synchronous FIFO data output after a propagation delay.
Claim 8
Dependent Claim
133 words
A circuit for matching data rates to transfer data between two asynchronous devices, comprising: an asynchronous FIFO that has a data input, a data output, and a control output indicating that a data word is available for outputting; a synchronizer, that has a control input and a control output, said control input connected to said asynchronous FIFO control output; and a synchronous FIFO, that has a data input, a control input and a data output, said synchronous FIFO control input connected to said synchronizer control output and said data input connected to said asynchronous FIFO data output; wherein asynchronous data signals inputted on said asynchronous FIFO data input from one of the asynchronous devices are outputted to the other of the asynchronous devices at said synchronous FIFO data output after a propagation delay.
Claim 9
Dependent Claim
21 words
A circuit, as set forth in claim 6, further comprising: means for controlling said asynchronous FIFO connected to said asynchronous FIFO.
Claim 10
Dependent Claim
21 words
A circuit, as set forth in claim 7, further comprising: means for controlling said synchronous FIFO connected to said synchronous FIFO.
Claim 11
Dependent Claim
21 words
A circuit, as set forth in claim 6, further comprising: means for controlling said synchronous FIFO connected to said synchronous FIFO.
Claim 12
Dependent Claim
141 words
A circuit for matching data rates to transfer data between two asynchronous devices, comprising: a synchronous FIFO, that has a data input, a data output and a control output, said control output indicating that said synchronous FIFO has a data word therein for transfer; a synchronizer, that has a control input and a control output, said synchronizer control input connected to said synchronous FIFO control output; and an asynchronous FIFO, that has a data input, a control input, and a data output, said asynchronous FIFO data input connected to said synchronous FIFO data output and said asynchronous FIFO control input connected to said synchronizer control output; wherein asynchronous data signals inputted on said synchronous FIFO data input from one of the asynchronous devices are outputted to the other of the asynchronous devices at said asynchronous FIFO output after a propagation delay.
Claim 13
Dependent Claim
141 words
A circuit for matching data rates to transfer data between two asynchronous devices, comprising: a synchronous FIFO, that has a data input, a data output and a control output, said control output indicating that said synchronous FIFO has a data word therein for transfer; a synchronizer, that has a control input and a control output, said synchronizer control input connected to said synchronous FIFO control output; and an asynchronous FIFO, that has a data input, a control input, and a data output, said asynchronous FIFO data input connected to said synchronous FIFO data output and said asynchronous FIFO control input connected to said synchronizer control output; wherein asynchronous data signals inputted on said synchronous FIFO data input from one of the asynchronous devices are outputted to the other of the asynchronous devices at said asynchronous FIFO output after a propagation delay.
Claim 14
Dependent Claim
21 words
A circuit, as set forth in claim 10, further comprising: means for controlling said asynchronous FIFO connected to said asynchronous FIFO.
Claim 15
Dependent Claim
21 words
A circuit, as set forth in claim 11, further comprising: means for controlling said synchronous FIFO connected to said synchronous FIFO.
Claim 16
Dependent Claim
21 words
A circuit, as set forth in claim 10, further comprising: means for controlling said synchronous FIFO connected to said synchronous FIFO.
Claim 17
Independent Claim
69 words
A method of transferring data between two asynchronous devices comprising the steps of: receiving data into an asynchronous FIFO from a first asynchronous device at a first rate; signaling an intermediate synchronizer that received data is available for outputting from said asynchronous FIFO; transferring said data into a synchronous FIFO under control of said intermediate synchronizer; and transmitting said data from said synchronous FIFO to a second asynchronous device.
Claim 18
Independent Claim
69 words
A method of transferring data between two asynchronous devices comprising the steps of: receiving data into an asynchronous FIFO from a first asynchronous device at a first rate; signaling an intermediate synchronizer that received data is available for outputting from said asynchronous FIFO; transferring said data into a synchronous FIFO under control of said intermediate synchronizer; and transmitting said data from said synchronous FIFO to a second asynchronous device.
Claim 19
Dependent Claim
30 words
The method as set forth in claim 14, wherein the step of transmitting said data from said synchronous FIFO to a second asynchronous device is at a second data rate.
Claim 20
Dependent Claim
36 words
The method as set forth in claim 15, further comprising the step of temporarily storing at least one word of data in said synchronous FIFO if said data rate is greater than said second data rate.
Claim 21
Dependent Claim
119 words
A circuit for matching data rates to transfer data between two asynchronous devices, comprising: an asynchronous FIFO having a first bi-directional data port, a second data bi-directional port, and a bi-directional control port; a synchronous FIFO having a first bi-directional port, a second bi-directional port, and a bi-directional control port, said first bi-directional data port of said synchronous FIFO coupled to said second bi-directional data port of said asynchronous FIFO; and a synchronizer having a first bi-directional control port and a second bi-directional control port, said first bi-directional control port of said synchronizer coupled to said bi-directional control port of said asynchronous FIFO and said second bi-directional control port coupled to said bi-directional control port of said synchronous FIFO.
Claim 22
Dependent Claim
119 words
A circuit for matching data rates to transfer data between two asynchronous devices, comprising: an asynchronous FIFO having a first bi-directional data port, a second data bi-directional port, and a bi-directional control port; a synchronous FIFO having a first bi-directional port, a second bi-directional port, and a bi-directional control port, said first bi-directional data port of said synchronous FIFO coupled to said second bi-directional data port of said asynchronous FIFO; and a synchronizer having a first bi-directional control port and a second bi-directional control port, said first bi-directional control port of said synchronizer coupled to said bi-directional control port of said asynchronous FIFO and said second bi-directional control port coupled to said bi-directional control port of said synchronous FIFO.
Claim 23
Dependent Claim
94 words
A circuit for matching data rates to transfer data between two asynchronous devices, comprising: an asynchronous FIFO having a data input, a data output, and a control output indicating that a data word is available for outputting; a synchronizer having a control input and a control output, said control input coupled to said asynchronous FIFO control output; and a synchronous FIFO having a data input, a control input and a data output, said synchronous FIFO control input coupled to said synchronizer control output and said data input coupled to said asynchronous FIFO data output.
Claim 24
Dependent Claim
94 words
A circuit for matching data rates to transfer data between two asynchronous devices, comprising: an asynchronous FIFO having a data input, a data output, and a control output indicating that a data word is available for outputting; a synchronizer having a control input and a control output, said control input coupled to said asynchronous FIFO control output; and a synchronous FIFO having a data input, a control input and a data output, said synchronous FIFO control input coupled to said synchronizer control output and said data input coupled to said asynchronous FIFO data output.
Claim 25
Dependent Claim
103 words
A circuit for matching data rates to transfer data between two asynchronous devices, comprising: a synchronous FIFO having a data input, a data output and a control output, said control output indicating that said synchronous FIFO has a data word therein for transfer; a synchronizer having a control input and a control output, said synchronizer control input coupled to said synchronous FIFO control output; and an asynchronous FIFO having a data input, a control input, and a data output, said asynchronous FIFO data input coupled to said synchronous FIFO data output and said asynchronous FIFO control input coupled to said synchronizer control output.
Claim 26
Dependent Claim
103 words
A circuit for matching data rates to transfer data between two asynchronous devices, comprising: a synchronous FIFO having a data input, a data output and a control output, said control output indicating that said synchronous FIFO has a data word therein for transfer; a synchronizer having a control input and a control output, said synchronizer control input coupled to said synchronous FIFO control output; and an asynchronous FIFO having a data input, a control input, and a data output, said asynchronous FIFO data input coupled to said synchronous FIFO data output and said asynchronous FIFO control input coupled to said synchronizer control output.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-01-07 | 2000-07-08 | 2001-01-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-01-07 | 2004-07-08 | 2005-01-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-01-07 | 2008-07-08 | 2009-01-07 | $7700.00 | Window Closed / Lapsed |