Patent US5880967A successfully refreshed from Google Patents.
US5880967A
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Minimization of circuit delay and power through transistor sizing
Assignee: Synopsys Inc
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Filing: 1995-05-01
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Granted: 1999-03-09
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Expires: 2015-05-01
Abstract
Abstract A method for minimizing signal delay and power consumption is provided. Through combined power simulation and delay analysis, iterative transistor resizing is performed based on a variety of factors including relative delay of associated circuit paths, nodal switching activities and association of transistors in channel-connected sets.
Inventors
- 👤 Henry Horng-Fei Jyu
- 👤 An-Chang Deng
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 19:31
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/32; G06F30/327; G06F2119/00; G06F2119/06
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
192 words
In a programmed digital computer, a method of minimizing signal delay and power consumption of a selected circuit, wherein the selected circuit includes a plurality of circuit paths constructed from transistors and nodes, said method comprising the steps of: determining a time delay of each path in said selected circuit, wherein a time delay of greatest value is associated with a critical path of said selected circuit; selecting a first transistor, said first transistor residing in a first path in said selected circuit having a first time delay; simulating operation of said selected circuit; counting state switches of a first node of said selected circuit during said simulation step, said first node being coupled to said first transistor; and resizing said first transistor based upon a number of state switches occurring at said first node, wherein said resizing step includes the steps of: sizing up said first transistor when said first time delay normalized to the time delay of greatest value exceeds a predetermined threshold value; and sizing down said first transistor when said first time delay normalized to the time delay of greatest value is less than said predetermined threshold value.
Claim 2
Dependent Claim
192 words
In a programmed digital computer, a method of minimizing signal delay and power consumption of a selected circuit, wherein the selected circuit includes a plurality of circuit paths constructed from transistors and nodes, said method comprising the steps of: determining a time delay of each path in said selected circuit, wherein a time delay of greatest value is associated with a critical path of said selected circuit; selecting a first transistor, said first transistor residing in a first path in said selected circuit having a first time delay; simulating operation of said selected circuit; counting state switches of a first node of said selected circuit during said simulation step, said first node being coupled to said first transistor; and resizing said first transistor based upon a number of state switches occurring at said first node, wherein said resizing step includes the steps of: sizing up said first transistor when said first time delay normalized to the time delay of greatest value exceeds a predetermined threshold value; and sizing down said first transistor when said first time delay normalized to the time delay of greatest value is less than said predetermined threshold value.
Claim 3
Dependent Claim
32 words
The method of claim 1 further comprising the steps of: estimating wiring capacitance of said first node in said selected circuit based upon fanin and fanout and area of said first node.
Claim 4
Dependent Claim
99 words
The method of claim 1 further comprising the step of: inputting a netlist of an original circuit into said computer, said original circuit including a plurality of circuit paths and transistors included in these paths; generating a scaling circuit from said netlist of said original circuit, said scaling circuit having transistor widths that are scaled values of transistor widths in said original circuit; generating a changing circuit from said netlist of said original circuit, said changing circuit having transistor widths that are uniform; and choosing said selected circuit from said original, scaling and changing circuits based on user-selected criteria.
Claim 5
Dependent Claim
19 words
The method of claim 3 wherein said user-selected criteria is power consumption of said original, scaling and changing circuits.
Claim 6
Dependent Claim
26 words
The method of claim 3 wherein said user-selected criteria is a cost function based on power, delay and area of said original, scaling and changing circuits.
Claim 7
Dependent Claim
18 words
The method of claim 3 wherein said user-selected criteria is delay of said original, scaling and changing circuits.
Claim 8
Dependent Claim
152 words
In a programmed digital computer, a method of minimizing signal delay and power consumption of a selected circuit, wherein the selected circuit includes a plurality of circuit paths constructed from transistors and nodes, said method comprising the steps of: determining a time delay of each path in said selected circuit, wherein a time delay of greatest value is associated with a critical path of said selected circuit; identifying all transistors that are channel connected in a pseudo gate within said selected circuit; determining an average ratio value associated with said pseudo gate based on individual ratio values associated with each of said all transistors, said ratio value being a function of time delays associated with one or more circuit paths; assigning said average ratio value to each of said all transistors in a data structure stored in a computer-readable medium; and resizing each of said all transistors using said average ratio value.
Claim 9
Dependent Claim
152 words
In a programmed digital computer, a method of minimizing signal delay and power consumption of a selected circuit, wherein the selected circuit includes a plurality of circuit paths constructed from transistors and nodes, said method comprising the steps of: determining a time delay of each path in said selected circuit, wherein a time delay of greatest value is associated with a critical path of said selected circuit; identifying all transistors that are channel connected in a pseudo gate within said selected circuit; determining an average ratio value associated with said pseudo gate based on individual ratio values associated with each of said all transistors, said ratio value being a function of time delays associated with one or more circuit paths; assigning said average ratio value to each of said all transistors in a data structure stored in a computer-readable medium; and resizing each of said all transistors using said average ratio value.
Claim 10
Dependent Claim
94 words
The method of claim 7 wherein said average ratio value comprises an average p-type ratio value and an average n-type ratio value and wherein said determining step comprises the steps of: determining an average p-type ratio value derived from individual ratio values associated with each of said all transistors that are p-type transistors; and determining an average n-type ratio value derived from individual ratio values associated with each of said all transistors that are n-type transistors, said p-type and n-type ratio values being functions of time delays associated with one or more circuit paths.
Claim 11
Dependent Claim
28 words
The method of claim 7 wherein said data structure comprises an array of transistor parameter records, each of said parameter records including a plurality of fields containing data.
Claim 12
Dependent Claim
99 words
The method of claim 7 further comprising the step of: inputting a netlist of an original circuit into said computer, said original circuit including a plurality of circuit paths and transistors included in these paths; generating a scaling circuit from said netlist of said original circuit, said scaling circuit having transistor widths that are scaled values of transistor widths in said original circuit; generating a changing circuit from said netlist of said original circuit, said changing circuit having transistor widths that are uniform; and choosing said selected circuit from said original, scaling and changing circuits based on user-selected criteria.
Claim 13
Dependent Claim
26 words
The method of claim 10 wherein said user-selected criteria is a cost function based on power, delay and area of said original, scaling and changing circuits.
Claim 14
Dependent Claim
19 words
The method of claim 10 wherein said user-selected criteria is power consumption of said original, scaling and changing circuits.
Claim 15
Dependent Claim
18 words
The method of claim 10 wherein said user-selected criteria is delay of said original, scaling and changing circuits.
Claim 16
Dependent Claim
108 words
In a programmed digital computer, a method of minimizing circuit signal delay and power consumption comprising the steps of: inputting into said computer a netlist of a first circuit, said first circuit including a plurality of circuit paths constructed from transistors and nodes; generating a second circuit based on a modification of transistor size in said first circuit; selecting a chosen circuit between said first and said second circuits based on circuit performance; resizing a first transistor in said chosen circuit based on path delay; performing a static timing analysis and power simulation of said chosen circuit; and terminating transistor resizing when performance degradation exceeds a predetermined threshold.
Claim 17
Dependent Claim
108 words
In a programmed digital computer, a method of minimizing circuit signal delay and power consumption comprising the steps of: inputting into said computer a netlist of a first circuit, said first circuit including a plurality of circuit paths constructed from transistors and nodes; generating a second circuit based on a modification of transistor size in said first circuit; selecting a chosen circuit between said first and said second circuits based on circuit performance; resizing a first transistor in said chosen circuit based on path delay; performing a static timing analysis and power simulation of said chosen circuit; and terminating transistor resizing when performance degradation exceeds a predetermined threshold.
Claim 18
Dependent Claim
22 words
The method of claim 14 wherein said predetermined threshold is based on a composite value of normalized power, delay and area values.
Claim 19
Dependent Claim
27 words
The method of claim 14 wherein said resizing step is further based on a number of state switches occurring at a node coupled to said first transistor.
Claim 20
Dependent Claim
102 words
The method of claim 14 wherein said resizing step includes the steps of: determining a time delay of each path in said chosen circuit, wherein said first transistor resides in a select path having a select time delay and a critical path of said chosen circuit has a time delay of greatest value; sizing up said first transistor when said select time delay normalized to the time delay of greatest value exceeds a predetermined threshold value; and sizing down said first transistor when said select time delay normalized to the time delay of greatest value is less than said predetermined threshold value.
Claim 21
Dependent Claim
18 words
The method of claim 14 wherein said resizing step includes selecting a cell from a predefined cell library.
Claim 22
Dependent Claim
95 words
The method of claim 14 wherein said resizing step includes: identifying all transistors that are channel connected with said first transistor in a pseudo gate; determining an average ratio value associated with said pseudo gate based on individual ratio values associated with each of said all transistors, said ratio value being a function of time delays associated with one or more circuit paths; assigning said average ratio value to each of said all transistor in a data structure stored in a computer-readable medium; and resizing each of said all transistors using said average ratio value.
Claim 23
Dependent Claim
28 words
The method of claim 19 wherein said data structure comprises an array of transistor parameter records, each of said parameter records including a plurality of fields containing data.
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2002-03-08 | 2002-09-07 | 2003-03-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-03-08 | 2006-09-07 | 2007-03-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-03-08 | 2010-09-07 | 2011-03-09 | $7700.00 | Window Closed / Lapsed |