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US5877046A
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Methods of forming semiconductor-on-insulator substrates
Assignee: Samsung Electronics Co Ltd
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Filing: 1997-04-09
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Granted: 1999-03-02
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Expires: 2017-04-09
Abstract
Abstract Methods of forming semiconductor-on-insulator substrates include the steps of forming a underlying semiconductor layer to electrically interconnect a plurality of SOI active regions and thereby prevent one or more of the active regions from "floating" relative to the other active regions. The reduction of floating body effects (FBE) improves the I-V characteristics of SOI devices including SOI MOSFETs. A method is provided which includes the steps of forming a second electrically insulating layer having a plurality of first openings therein, on a first face of a first semiconductor substrate. A first semiconductor layer is then formed on the second electrically insulating layer so that direct electrical connections are made between the first semiconductor layer and the first semiconductor substrate. A first electrically insulating layer is then formed on the first semiconductor layer. This first electrically insulating layer is then planarized and bonded to a second semiconductor substrate. The composite intermediate structure is then inverted and followed by the step of planarizing a second face of the first semiconductor substrate to define a second semiconductor layer. A plurality of spaced semiconductor active regions are then defined in the second semiconductor layer by using field oxide isolation techniques to consume the entire thickness of the second semiconductor layer at predetermined spaced locations. This step essentially isolates the active regions from each other, however, these active regions do not "float" because they are electrically connected to each other indirectly through the underlying first semiconductor layer.
Inventors
- 👤 Sun-il Yu
- 👤 Woo-tag Kang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 13:53
CPC Classifications
H; H10; H10P; H10P10/00; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/031; H10D30/0321; H10D30/0323; H10D30/60; H10D30/67; H10D30/6704; H10D30/6708; H10D30/6758; H10P90/00; H10P90/19; H10P90/1904; H10P90/1906; H10W; H10W10/00; H10W10/01; H10W10/061; H10W10/10; H10W10/181; H10P90/1912; H10W10/011; H10W10/012; H10W10/13; Y; Y10; Y10S; Y10S438/00; Y10S438/977
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
90 words
A method of forming a semiconductor-on-insulator field effect transistor, comprising the steps of: forming a substrate comprising a first electrically insulating layer having an insulating mesa extending therefrom, a first semiconductor layer covering the insulating mesa and a second electrically insulating layer having a first opening therein which exposes a first portion of the first semiconductor layer extending opposite the insulating mesa; and forming a field effect transistor having a channel region directly electrically connected to the first semiconductor layer at the first opening in the second electrically insulating layer.
Claim 2
Independent Claim
90 words
A method of forming a semiconductor-on-insulator field effect transistor, comprising the steps of: forming a substrate comprising a first electrically insulating layer having an insulating mesa extending therefrom, a first semiconductor layer covering the insulating mesa and a second electrically insulating layer having a first opening therein which exposes a first portion of the first semiconductor layer extending opposite the insulating mesa; and forming a field effect transistor having a channel region directly electrically connected to the first semiconductor layer at the first opening in the second electrically insulating layer.
Claim 3
Independent Claim
148 words
A method of forming a semiconductor-on-insulator field effect transistor, comprising the steps of: forming a substrate comprising a first electrically insulating layer having an insulating mesa extending therefrom, a first semiconductor layer covering the insulating mesa and a second electrically insulating layer having a first opening therein which exposes a first portion of the first semiconductor layer extending opposite the insulating mesa: forming a field effect transistor having a channel region electrically coupled to the first semiconductor layer at the first opening in the second electrically insulating layer forming a contact hole in the second electrically insulating layer to expose a second portion of the first semiconductor layer; forming a drain contact ohmically connected to a drain region of the field effect transistor; and forming a source contact ohmically connected to a source region of the field effect transistor and the second portion of the first semiconductor layer.
Claim 4
Independent Claim
148 words
A method of forming a semiconductor-on-insulator field effect transistor, comprising the steps of: forming a substrate comprising a first electrically insulating layer having an insulating mesa extending therefrom, a first semiconductor layer covering the insulating mesa and a second electrically insulating layer having a first opening therein which exposes a first portion of the first semiconductor layer extending opposite the insulating mesa: forming a field effect transistor having a channel region electrically coupled to the first semiconductor layer at the first opening in the second electrically insulating layer forming a contact hole in the second electrically insulating layer to expose a second portion of the first semiconductor layer; forming a drain contact ohmically connected to a drain region of the field effect transistor; and forming a source contact ohmically connected to a source region of the field effect transistor and the second portion of the first semiconductor layer.
Claim 5
Independent Claim
163 words
A method of forming a semiconductor-on-insulator field effect transistor, comprising the steps of: forming a substrate comprising a first electrically insulating layer having an insulating mesa extending therefrom, a first semiconductor layer covering the insulating mesa and a second electrically insulating layer having a first opening therein which exposes a first portion of the first semiconductor layer extending opposite the insulating mesa, and forming a field effect transistor having a channel region electrically coupled to the first semiconductor layer at the first opening in the second electrically insulating layer, and wherein said step of forming a substrate comprises the steps of: forming the second electrically insulating layer on a first face of a semiconductor substrate; patterning the second electrically insulating layer so that the first opening exposes the first face of the semiconductor substrate; forming the first semiconductor layer on the second electrically insulating layer and in the first opening therein; and forming the first electrically insulating layer on the first semiconductor layer.
Claim 6
Independent Claim
163 words
A method of forming a semiconductor-on-insulator field effect transistor, comprising the steps of: forming a substrate comprising a first electrically insulating layer having an insulating mesa extending therefrom, a first semiconductor layer covering the insulating mesa and a second electrically insulating layer having a first opening therein which exposes a first portion of the first semiconductor layer extending opposite the insulating mesa, and forming a field effect transistor having a channel region electrically coupled to the first semiconductor layer at the first opening in the second electrically insulating layer, and wherein said step of forming a substrate comprises the steps of: forming the second electrically insulating layer on a first face of a semiconductor substrate; patterning the second electrically insulating layer so that the first opening exposes the first face of the semiconductor substrate; forming the first semiconductor layer on the second electrically insulating layer and in the first opening therein; and forming the first electrically insulating layer on the first semiconductor layer.
Claim 7
Dependent Claim
36 words
The method of claim 3, wherein said step of forming a field effect transistor is preceded by the step of planarizing the first electrically insulating layer at a surface thereof extending opposite the first semiconductor layer.
Claim 8
Dependent Claim
15 words
The method of claim 3, wherein the insulating mesa is self-aligned to the first opening.
Claim 9
Dependent Claim
54 words
The method of claim 5, wherein said step of forming a field effect transistor is preceded by the step of forming field oxide isolation regions in the semiconductor substrate to define an active region therein which is electrically connected to the first semiconductor layer at the first opening in the second electrically insulating layer.
Claim 10
Dependent Claim
37 words
The method of claim 6, wherein said step of forming field oxide isolation regions in the semiconductor substrate is preceded by the step of planarizing a second face of the semiconductor substrate extending opposite the first face.
Claim 11
Dependent Claim
24 words
The method of claim 7, wherein said step of forming a field effect transistor comprises forming a field effect transistor in the active region.
Claim 12
Dependent Claim
25 words
The method of claim 8, wherein said step of forming a field effect transistor comprises forming an insulated gate electrode on the planarized second face.
Claim 13
Dependent Claim
47 words
The method of claim 9, wherein said step of forming a field effect transistor comprises forming a field effect transistor in the active region so that the source and channel regions of the field effect transistor form rectifying and nonrectifying junctions with the first semiconductor layer, respectively.
Claim 14
Dependent Claim
44 words
The method of claim 9, wherein said step of forming a field effect transistor comprises forming a field effect transistor in the active region so that the source and channel regions of the field effect transistor form nonrectifying junctions with the first semiconductor layer.
Claim 15
Independent Claim
154 words
A method of forming a semiconductor-on-insulator substrate, comprising the steps of: forming a second electrically insulating layer on a first face of a first semiconductor substrate; patterning the second electrically insulating layer to define a plurality of first openings therein which expose respective portions of the first face of the semiconductor substrate; forming a first semiconductor layer on the second electrically insulating layer and in the plurality of first openings therein; forming a first electrically insulating layer on the first semiconductor layer; planarizing a second face of the first semiconductor substrate to define a second semiconductor layer extending opposite the second electrically insulating layer and the plurality of first openings therein; and forming field oxide isolation regions at the planarized second face to convert the second semiconductor layer into a plurality of semiconductor active regions which are electrically connected to the first semiconductor layer at respective first openings in the second electrically insulating layer.
Claim 16
Independent Claim
154 words
A method of forming a semiconductor-on-insulator substrate, comprising the steps of: forming a second electrically insulating layer on a first face of a first semiconductor substrate; patterning the second electrically insulating layer to define a plurality of first openings therein which expose respective portions of the first face of the semiconductor substrate; forming a first semiconductor layer on the second electrically insulating layer and in the plurality of first openings therein; forming a first electrically insulating layer on the first semiconductor layer; planarizing a second face of the first semiconductor substrate to define a second semiconductor layer extending opposite the second electrically insulating layer and the plurality of first openings therein; and forming field oxide isolation regions at the planarized second face to convert the second semiconductor layer into a plurality of semiconductor active regions which are electrically connected to the first semiconductor layer at respective first openings in the second electrically insulating layer.
Claim 17
Dependent Claim
63 words
The method of claim 12, wherein said step of planarizing the second face of the first semiconductor substrate comprises planarizing the second face of the first semiconductor substrate to define a second semiconductor layer having a first thickness; and wherein said step of forming field oxide isolation regions comprises forming field oxide isolation regions having a second thickness greater than the first thickness.
Claim 18
Dependent Claim
30 words
The method of claim 13, wherein said step of planarizing the second face of the first semiconductor substrate is preceded by the step of planarizing the first electrically insulating layer.
Claim 19
Dependent Claim
32 words
The method of claim 14, wherein said step of planarizing the first electrically insulating layer is followed by the step of bonding a second semiconductor substrate to the first electrically insulating layer.
Claim 20
Dependent Claim
23 words
The method of claim 15, further comprising the steps of forming at least one semiconductor device in each of the semiconductor active regions.
Claim 21
Dependent Claim
79 words
The method of claim 16, wherein said step of forming at least one semiconductor device comprises forming a field effect transistor in one of the semiconductor active regions so that the source and channel regions of the field effect transistor form semiconductor junctions selected from the group consisting of rectifying and nonrectifying semiconductor junctions, with the first semiconductor layer, but the drain region of the field effect transistor does not form a semiconductor junction with the first semiconductor layer.
Claim 22
Dependent Claim
53 words
The method of claim 17, wherein said step of forming a field effect transistor comprises the steps of forming a contact hole extending through one of the field oxide isolation regions and the second electrically insulating layer to expose the first semiconductor layer; and then forming a source contact in the contact hole.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-03-01 | 2002-08-31 | 2003-03-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-03-01 | 2006-08-31 | 2007-03-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-03-01 | 2010-08-31 | 2011-03-02 | $7700.00 | Window Closed / Lapsed |