Patent US5875135A successfully refreshed from Google Patents.
US5875135A
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Characterization of self time circuit
Assignee: Intel Corp
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Filing: 1996-10-18
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Granted: 1999-02-23
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Expires: 2016-10-18
Abstract
Abstract Method and apparatus for characterization of a self timed circuit in an integrated circuit such as a sense amplifier in a memory. A software controlled testability feature is added to the integrated circuit permitting the sense amplifier to be enabled earlier in time following word line activation. In particular, a replacement timing circuit activated by a falling clock edge causes the sense amplifier enable signal to become clock frequency sensitive. The clock frequency is software controlled and parity checking provides a failure detection mechanism. A plurality of the integrated circuit are tested to provide the characterization.
Inventors
- 👤 Shekhar Patwardhan
- 👤 Tsafrir Israeli
- 👤 Eitan Rosen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 11:08
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/02; G11C29/026; G11C29/028; G11C29/04; G11C29/50; G11C29/50012
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
89 words
A method for improving the performance of a circuit incorporated in an integrated circuit comprising: providing a plurality of bypassable timing elements coupled to the circuit, such that the performance of the circuit is predicted to improve as one or more of the timing elements is bypassed; testing the circuit in a manner which simulates selectively bypassing the elements; determining from the testing the number of elements that should be bypassed to improved the performance of the circuits; and bypassing the number of elements determined from the preceding step.
Claim 2
Independent Claim
89 words
A method for improving the performance of a circuit incorporated in an integrated circuit comprising: providing a plurality of bypassable timing elements coupled to the circuit, such that the performance of the circuit is predicted to improve as one or more of the timing elements is bypassed; testing the circuit in a manner which simulates selectively bypassing the elements; determining from the testing the number of elements that should be bypassed to improved the performance of the circuits; and bypassing the number of elements determined from the preceding step.
Claim 3
Dependent Claim
35 words
The method defined by claim 1 wherein a plurality of integrated circuits incorporating the circuit are subjected to the testing in order to make the determination on the number of elements that should be bypassed.
Claim 4
Dependent Claim
33 words
The method defined by claim 1 wherein the step of bypassing the elements comprises the making of a mask change to at least one mask used in the fabrication of the integrated circuit.
Claim 5
Dependent Claim
23 words
The method defined by claim 1 including the additional step of verifying the performance of the circuit after the elements have been bypassed.
Claim 6
Independent Claim
148 words
A method for characterizing a memory circuit such that the time between the enablement of a word line and the enablement of a sense amplifier may be reduced comprising: providing a plurality of bypassable delay elements coupled to the sense amplifier, such that as the elements are bypassed the time between the enablement of the word line and the sense amplifier is reduced; providing a timing circuit which is enabled in a test mode and which controllably causes the time between the enablement of the word line and the enablement of the sense amplifier to be reduced; providing a mechanism for detecting sensing errors in the sense amplifier; testing a plurality of the memory circuit so as to determine the number of the timing elements that should be bypassed to increase the performance of the memory circuit; and bypassing the number of elements determined from the preceding step.
Claim 7
Independent Claim
148 words
A method for characterizing a memory circuit such that the time between the enablement of a word line and the enablement of a sense amplifier may be reduced comprising: providing a plurality of bypassable delay elements coupled to the sense amplifier, such that as the elements are bypassed the time between the enablement of the word line and the sense amplifier is reduced; providing a timing circuit which is enabled in a test mode and which controllably causes the time between the enablement of the word line and the enablement of the sense amplifier to be reduced; providing a mechanism for detecting sensing errors in the sense amplifier; testing a plurality of the memory circuit so as to determine the number of the timing elements that should be bypassed to increase the performance of the memory circuit; and bypassing the number of elements determined from the preceding step.
Claim 8
Dependent Claim
40 words
The method defined by claim 5 wherein the frequency of a memory cycle for the memory circuit is reduced thereby causing the time between the enablement of the word line and the enablement of the sense amplifier to be reduced.
Claim 9
Dependent Claim
16 words
The method defined by claim 5 wherein a parity bit is used to detect the errors.
References Cited (Backward Citations)
US5442799A
Cited
US4926387A
Cited
US5031141A
Cited
US5471430A
Cited
US5452261A
Cited
US5729160A
Cited
US5729503A
Cited
US5633828A
Cited
US5559745A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-02-22 | 2002-08-24 | 2003-02-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-02-22 | 2006-08-24 | 2007-02-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-02-22 | 2010-08-24 | 2011-02-23 | $7700.00 | Window Closed / Lapsed |