Self-timed circuit control device and method

Claim 2

A self-timed electric circuit, comprising: a first electric circuit portion having a plurality of output terminals with corresponding output signals, each of the output signals representing a logic state, the first electric circuit portion having a switch means for enabling said first electric circuit portion when the switch means is turned on and for disabling said first electric circuit portion when the switch means is turned off an external input terminal, the external input terminal having a corresponding external input signal; a second electric circuit portion having: (a) sensing means for detecting a change in any one of said output signals of the first electric circuit portion, the change corresponding to a change in the logic state represented by said any one output signal, the sensing means having input terminals and an output terminal, said input terminals each being connected to a respective output terminal of said first circuit portion, each of said connected input terminals of the sensing means receiving an input signal constituting the respective output signal corresponding to each output terminal of the first electric circuit portion, the sensing means constituting means for performing the equivalent of a NAND logic function on each logic state corresponding to the respective input signal of the sensing means; and (b) immobilizing means responsive to said sensing means for disabling the first electric circuit portion by turning off the switch means, the immobilizing means having an input terminal connected to the output terminal of the sensing means and having an output terminal connected to the switch means of said first electric circuit portion; wherein the immobilizing means disables the first electric circuit portion when the sensing means detects said change in the logic state represented by said any one output signal of the first electric circuit portion and when said any one output signal has acquired a value corresponding to a predetermined logic state, the sensing means constituting means for overriding the effect of the external input signal to the switch means of the first electric circuit portion, which external input signal would otherwise be effective to turn on the switch means.

Claim 3

The circuit of claim 1, wherein: (a) the switch means of the first electric circuit portion is turned on by a signal with a value corresponding to logic 1 and is turned off by a signal with a value corresponding to logic 0; and (b) the immobilizing means causes a signal with a value corresponding to logic 0 to be input to the switch means at a time when the external input signal has a value corresponding to logic 1.

Claim 4

The circuit of claim 2, wherein: (a) the external input signal to the switch means is a generally square periodic wave form that alternates between values corresponding to logic 1 and logic 0; (b) the immobilizing means has a second input terminal connected to the external input terminal and receiving the external input signal; (c) the immobilizing means performs the equivalent of a NOR function on logic states represented by signals received by the input terminals of the immobilizing means; and (d) the predetermined logic state of any one of said input signals received by the said connected input terminals of the sensing means is logic 0.

Claim 5

The circuit of claim 1, wherein the predetermined logic state of any one of said input signals received by the said connected input terminals of the sensing means is logic 0.

Claim 6

The circuit of claim 1, wherein the first electric circuit portion is a read sense amplifier in a dynamic random access memory (DRAM).

Claim 7

The circuit of claim 5, wherein the sense amplifier is a CMOS amplifier.

Claim 8

The circuit of claim 1, wherein the sensing means is a NAND logic gate.

Claim 9

A self-timed electric circuit, comprising: a first electric circuit portion which is part of a random access memory and having a plurality of first address lines therefor, the first electric circuit portion having multiplexed address buffers connected to predecoders, the first electric circuit portion having a plurality of output terminals with corresponding output signals and having a plurality of latch means with corresponding latch controls for engaging and disengaging each latch means, the latch means constituting means for latching output states of said output signals when the latch means are engaged, each of the latch means being connected respectively to each of the first address lines, said first address lines each being connected to a respective predecoder at inputs of said latch means; a plurality of second address lines for the random access memory, each of the second address lines being connected, at inputs of said latch means, to a respective first address line of the first electric circuit portion; a second electric circuit portion having: (a) sensing means having a plurality of input terminals and an output terminal, the input terminals each being connected, at outputs of said latch means, to a respective output terminal of the first electric circuit portion, the sensing means constituting means for performing the equivalent of an OR logic function on the output states of said output signals; (b) activating means responsive to the sensing means for engaging the latch means by activating the latch controls thereof, the activating means having an input terminal connected to the output terminal of the sensing means, and having an output terminal connected to each of said first address lines at the latch control of the latch means; wherein the activating means engages the latch means to thereby latch the output states of said output signals when the sensing means detects a change in the output state of any one of said output signals and said any one output signal has acquired an output state corresponding to a predetermined logic state, and wherein said latching of the output states of the output signals frees the address buffers and predecoders to perform an addressing function by means of said second address lines while the latch means are engaged.

Claim 10

A self-timed electric circuit, comprising: a first electric circuit portion which is part of a random access memory and having a plurality of first address lines therefor, the first electric circuit portion having multiplexed address buffers connected to predecoders, the first electric circuit portion having a plurality of output terminals with corresponding output signals and having a plurality of latch means with corresponding latch controls for engaging and disengaging each latch means, the latch means constituting means for latching output states of said output signals when the latch means are engaged, each of the latch means being connected respectively to each of the first address lines, said first address lines each being connected to a respective predecoder at inputs of said latch means; a plurality of second address lines for the random access memory, each of the second address lines being connected, at inputs of said latch means, to a respective first address line of the first electric circuit portion; a second electric circuit portion having: (a) sensing means having a plurality of input terminals and an output terminal, the input terminals each being connected, at outputs of said latch means, to a respective output terminal of the first electric circuit portion, the sensing means constituting means for performing the equivalent of an OR logic function on the output states of said output signals; (b) activating means responsive to the sensing means for engaging the latch means by activating the latch controls thereof, the activating means having an input terminal connected to the output terminal of the sensing means, and having an output terminal connected to each of said first address lines at the latch control of the latch means; wherein the activating means engages the latch means to thereby latch the output states of said output signals when the sensing means detects a change in the output state of any one of said output signals and said any one output signal has acquired an output state corresponding to a predetermined logic state, and wherein said latching of the output states of the output signals frees the address buffers and predecoders to perform an addressing function by means of said second address lines while the latch means are engaged.

Claim 11

The circuit of claim 8 wherein: (a) the latch means of the first electric circuit portion are activated by a signal with a value corresponding to logic 1; and (b) the activating means causes a signal with a value corresponding to logic 1 to be input to the latch means.

Claim 12

The circuit of claim 9, wherein the predetermined logic state of said any one output signal is logic 1.

Claim 13

The circuit of claim 8 wherein the predetermined logic state of said any one output signal is logic 1.

Claim 14

The circuit of claim 8, wherein the random access memory is a dynamic random access memory DRAM.

Claim 15

The circuit of claim 12, wherein the DRAM is implemented in CMOS.

Claim 16

The circuit of claim 8, wherein both the sensing means and the activating means are implemented with one OR logic function.

Claim 17

The circuit of claim 8, wherein the latch means includes a pass gate connected to a pair of cross-coupled inverters.

Claim 18

A self-timed control mechanism for a CMOS sense amplifier having two output terminals and a switch transistor biased for turning the sense amplifier on and off in response to signals with values corresponding respectively to logic 1 and 0, the mechanism comprising: (a) a NAND logic gate having two input terminals and an output terminal, each input terminal being connected to a respective sense amplifier output terminal that is precharged to logic 1; (b) a NOR logic gate having first and second input terminals and an output terminal, the first input terminal being connected to the output terminal of the NAND gate and the output terminal being connected to a gate of the switch transistor; and (c) an inverting logic gate having an input terminal for receiving an externally generated generally square periodic waveform whose value alternates between values corresponding to logic 1 and logic 0, and an output terminal that is connected to the second input terminal of the NOR gate.

Claim 19

A self-timed control mechanism for a CMOS sense amplifier having two output terminals and a switch transistor biased for turning the sense amplifier on and off in response to signals with values corresponding respectively to logic 1 and 0, the mechanism comprising: (a) a NAND logic gate having two input terminals and an output terminal, each input terminal being connected to a respective sense amplifier output terminal that is precharged to logic 1; (b) a NOR logic gate having first and second input terminals and an output terminal, the first input terminal being connected to the output terminal of the NAND gate and the output terminal being connected to a gate of the switch transistor; and (c) an inverting logic gate having an input terminal for receiving an externally generated generally square periodic waveform whose value alternates between values corresponding to logic 1 and logic 0, and an output terminal that is connected to the second input terminal of the NOR gate.

Claim 20

A self-timed feedback control mechanism for latching the logic states of address lines in a CMOS DRAM, the mechanism comprising: (a) a plurality of row address lines; (b) a plurality of column address lines; (c) a plurality of latch means corresponding to each of the row address lines and connected thereto, said latch means having a latch control for engaging and disengaging the latch means; (d) an OR logic gate having a plurality of input terminals and an output terminal, the input terminals each being connected, at outputs of said latch means, to a respective row address line, the output terminal being connected to the latch control of said latch means; wherein the column address lines are each respectively connected to the row address lines at inputs of said latch means, and the latch means are activated to latch the respective logic states of said corresponding row address lines when the said output of the OR logic gate signals a change in logic state of one of said row address lines which results in a value thereof corresponding to a predetermined logic state, and wherein the column address lines perform an addressing function while the latch means are activated.

Claim 21

A self-timed feedback control mechanism for latching the logic states of address lines in a CMOS DRAM, the mechanism comprising: (a) a plurality of row address lines; (b) a plurality of column address lines; (c) a plurality of latch means corresponding to each of the row address lines and connected thereto, said latch means having a latch control for engaging and disengaging the latch means; (d) an OR logic gate having a plurality of input terminals and an output terminal, the input terminals each being connected, at outputs of said latch means, to a respective row address line, the output terminal being connected to the latch control of said latch means; wherein the column address lines are each respectively connected to the row address lines at inputs of said latch means, and the latch means are activated to latch the respective logic states of said corresponding row address lines when the said output of the OR logic gate signals a change in logic state of one of said row address lines which results in a value thereof corresponding to a predetermined logic state, and wherein the column address lines perform an addressing function while the latch means are activated.

Claim 22

The self-timed feedback control mechanism according to claim 17, wherein the CMOS DRAM has multiplexed address buffers connected to predecoders, said row address lines each being connected to a respective predecoder at inputs of said latch means.