Nonvolatile semiconductor memory device including potential generating circuit

Claim 2

A nonvolatile semiconductor memory device comprising: a semiconductor substrate having a P-conductivity type region; a P-channel transistor connected between a first terminal supplied with a first potential and said P-conductivity type region; first N-channel transistor connected between a second terminal supplied with a second potential and said P-conductivity type region; stacked gate memory cells formed on said P-conductivity type region; and a second N-channel transistor formed on said substrate, said second N-channel transistor being electrically separated from said P-conductivity type region by a double well structure.

Claim 3

A nonvolatile semiconductor memory device according to claim 1, wherein said first potential is a positive power supply potential which is the same as a potential supplied to drains of said stacked gate memory cells during a write operation.

Claim 4

A nonvolatile semiconductor memory device according to claim 1, wherein said first potential is a positive power supply potential which is the same as a potential supplied to gates of said stacked gate memory cells during a write operation.

Claim 5

A nonvolatile semiconductor memory device according to claim 1, wherein a back gate of said P-channel transistor is connected to said first terminal and a back gate of said first N-channel transistor is connected to said second terminal.

Claim 6

A nonvolatile semiconductor memory device according to claim 1, wherein said second potential is ground potential.

Claim 7

A nonvolatile semiconductor memory device according to claim 1, wherein said P-channel transistor is formed in an N-conductivity type well formed in said P-condutivity type region.

Claim 8

A nonvolatile semiconductor memory device according to claim 1, wherein said first N-channel transistor is formed on said semiconductor substrate and electrically separated from said P-conductivity type region by a double well structure.

Claim 9

A nonvolatile semiconductor memory device according to claim 1, further comprising a metal layer formed on a surface area of said semiconductor substrate, which is opposite to a surface area in which said P-conductivity type region, said P-condcutivity type transistor, said first N-channel transistor, said stacked gate memory cells, and said second N-channel transistor are formed.

Claim 10

A nonvolatile semiconductor memory device comprising: a semiconductor substrate having a region of a first conductivity type; a first transitor having a channel of the first conductivity type, said first transistor connected between a first terminal supplied with a first potential and siad region of the first conductivity type; a second transistor having a channel of a second conductivity type, said second transistor connected between a second terminal supplied with a second potential and siad region of the first conductivity type; nonvolatile memory cells formed on said region of the first conductivity type; and a third transistor having a channel of the second conductivity type, said third transistor formed on said semiconductor substrate and said third transistor being electrically separated from said region of the frist conductivity type by a double well structure.

Claim 11

A nonvolatile semiconductor memory device comprising: a semiconductor substrate having a region of a first conductivity type; a first transitor having a channel of the first conductivity type, said first transistor connected between a first terminal supplied with a first potential and siad region of the first conductivity type; a second transistor having a channel of a second conductivity type, said second transistor connected between a second terminal supplied with a second potential and siad region of the first conductivity type; nonvolatile memory cells formed on said region of the first conductivity type; and a third transistor having a channel of the second conductivity type, said third transistor formed on said semiconductor substrate and said third transistor being electrically separated from said region of the frist conductivity type by a double well structure.

Claim 12

A nonvolatile semiconductor memory device according to claim 9, wherein said first potential is a positive power supply potential which is the same as a potential supplied to drains of said nonvolatile memory cells during a write operation.

Claim 13

A nonvolatile semiconducutor memory device according to claim 9, wherein said first potential is a positive power supply potential which is the same as a potential supplied to gates of said nonvolatile memory cells during a write operation.

Claim 14

A nonvolatile semiconductor memory device according to claim 9, wherein a back gate of said first transistor is connected to said first terminal and a back gate of said second transistor is connected to said second terminal.

Claim 15

A nonvolatile semicondcutor memory device according to claim 9, wherin said second potential is ground potential.

Claim 16

A nonvolatile semiconductor memory device according to claim 9, wherein said first transistor is formed in a well of the second conductivity type formed in said region of the first conductivity type.

Claim 17

A nonvolatile semiconductor memory device according to claim 9, wherein said second transistor is formed on said semiconductor substrate and is electrically separated from said region of the first conductivity type by a double well structure.

Claim 18

A nonvolatile semiconductor memory device according to claim 9, further comprising a metal layer formed on a surface area of said semiconductor substrate, which is opposite to a surface area in which said region of the first conductivity type, said first transistor, said second transistor, said stacked gate memory cells, and said third transistor are formed.

Claim 19

A nonvolatile semiconductor memory device according to claim 9, wherein said nonvolatile memory cells are stacked gate memory cells.

Claim 20

A nonvolatile semiconductor memory device, comprising: a semiconductor substrate having a region of a first conductivity type; nonvolatile memory cells formed on said region of the first conductivity type; a first transitior for a peripheral circuit of said nonvolatile semiconductor memory device having a channel of a second conductivity type, said first transistor being electrically separated form said region of the first conductivity type by a double well structure; and a potential generating circuit for generating a potential applied to said region of the first conductivity type, said potential generating circuit comprising: a second transistor having a channel of the first conductivity type, a first end connected to a first potential, a second end connected to said region of the first conductivity type, and a gate supplied with an erase signal; and a third transistor having a channel of the second conductivity type, a first end connected to a second potential, a second end connected to said region of the first conductivity type and a gate supplied with the erase signal.

Claim 21

A nonvolatile semiconductor memory device, comprising: a semiconductor substrate having a region of a first conductivity type; nonvolatile memory cells formed on said region of the first conductivity type; a first transitior for a peripheral circuit of said nonvolatile semiconductor memory device having a channel of a second conductivity type, said first transistor being electrically separated form said region of the first conductivity type by a double well structure; and a potential generating circuit for generating a potential applied to said region of the first conductivity type, said potential generating circuit comprising: a second transistor having a channel of the first conductivity type, a first end connected to a first potential, a second end connected to said region of the first conductivity type, and a gate supplied with an erase signal; and a third transistor having a channel of the second conductivity type, a first end connected to a second potential, a second end connected to said region of the first conductivity type and a gate supplied with the erase signal.