EP0525678A2
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EP
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Nonvolatile semiconductor memory device having row decoder
Assignee: Toshiba Corp
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Filing: 1992-07-24
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Granted: —
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Expires: 2012-07-24
Abstract
Abstract A nonvolatile semiconductor memory device is provided in which a negative voltage is applied to a gate electrode of a memory cell transistor (11) during an erase mode. The memory device includes a row decoder circuit (2) having an N-channel transistor (24) connected to a word line (12). The N-channel transistor (24) is provided on a P-type well region (33) of a semiconductor substrate (30). A negative voltage (V bb ) is applied to the P-type well region (33) during the erase mode, while ground potential is applied thereto during another modes.
Inventors
- 👤 Shigeru C/O Intellectual Property Div. Atsumi
- 👤 Sumio c/o Intellectual Property Div. Tanaka
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-04 14:23
CPC Classifications
G; G11; G11C; G11C16/00; G11C8/00; G11C8/08; G11C16/02; G11C16/06; G11C16/08; G11C16/10; G11C16/14
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
183 words
A nonvolatile semiconductor memory device including a semiconductor substrate (30) having a P-type well region (33), an array (1) of memory cell transistors (11) arranged in an X-Y matrix of rows and columns on the semiconductor substrate (30), word lines (12) commonly connected to gates of the memory cell transistors (11) arranged in a row direction of the array (1), bit lines (13) commonly connected to drains of the memory cell transistors (11) arranged in a column direction of the array (1), and row decoder circuit (2) for applying a negative voltage (V bb ) to the word lines (12) during an erase mode. characterized in that the row decoder circuit includes an N-channel transistor (24) provided on the P-type well region (33) and electrically connected to each of the word lines (12), that a source region of the N-channel transistor (24) is electrically connected to the P-type well region (33), and that a negative voltage (V bb ) is applied to the P-type well region (33) during the erase mode while ground potential (V ss ) is applied thereto during another modes.
Claim 2
Dependent Claim
183 words
A nonvolatile semiconductor memory device including a semiconductor substrate (30) having a P-type well region (33), an array (1) of memory cell transistors (11) arranged in an X-Y matrix of rows and columns on the semiconductor substrate (30), word lines (12) commonly connected to gates of the memory cell transistors (11) arranged in a row direction of the array (1), bit lines (13) commonly connected to drains of the memory cell transistors (11) arranged in a column direction of the array (1), and row decoder circuit (2) for applying a negative voltage (V bb ) to the word lines (12) during an erase mode. characterized in that the row decoder circuit includes an N-channel transistor (24) provided on the P-type well region (33) and electrically connected to each of the word lines (12), that a source region of the N-channel transistor (24) is electrically connected to the P-type well region (33), and that a negative voltage (V bb ) is applied to the P-type well region (33) during the erase mode while ground potential (V ss ) is applied thereto during another modes.
Claim 3
Dependent Claim
30 words
The nonvolatile semiconductor memory device according to claim 1, characterized in that the semiconductor substrate (30) is comprised of a P-type semiconductor substrate connected to ground potential (V s s).
Claim 4
Dependent Claim
32 words
The nonvolatile semiconductor memory device according to claim 2, characterized in that the P-type semiconductor substrate (30) has an N-type well region (31) in which the P-type well region (33) is provided.
Claim 5
Dependent Claim
26 words
The nonvolatile semiconductor memory device according to claim 2, characterized in that the memory cell transistors (11) are directly provided on the P-type semiconductor substrate (30).
Claim 6
Dependent Claim
30 words
The nonvolatile semiconductor memory device according to claim 1, characterized in that the source region (34) of the N-channel transistor (24) is connected to a negative charge pump circuit (10).
Claim 7
Dependent Claim
30 words
The nonvolatile semiconductor memory device according to claim 1, characterized in that a drain region (35) of the N-channel transistor (24) is connected to each of the word lines (12).
Claim 8
Dependent Claim
31 words
The nonvolatile semiconductor memory device according to claim 1, characterized in that the row decoder circuit (2) includes a CMOS inverter (22) controlled by the output of a NAND gate (21).
Claim 9
Dependent Claim
22 words
The nonvolatile semiconductor memory device according to claim 7, characterized in that the CMOS inverter (22) provides a word line driver circuit.
Claim 10
Dependent Claim
29 words
The nonvolatile semiconductor memory device according to claim 7, characterized in that the CMOS inverter (22) includes a P-channel transistor (23) connected in series with the N-channel transistor (24).
Claim 11
Dependent Claim
37 words
The nonvolatile semiconductor memory device according to claim 7, characterized in that the row decoder circuit (2) includes a transfer gate (41) controlled by an output of the CMOS inverter (22) and the NAND gate (21), respectively.
Claim 12
Dependent Claim
26 words
The nonvolatile semiconductor memory device according to claim 10, characterized in that the transfer gate (41) is connected in series with the N-channel transistor (24, 42).
Claim 13
Dependent Claim
31 words
The nonvolatile semiconductor memory device according to claim 10, characterized in that the transfer gate (41) is comprised of N- and P-channel transistors (44, 43) connected in parallel to each other.
Claim 14
Dependent Claim
26 words
The nonvolatile semiconductor memory device according to claim 11, characterized in that the N-channel transistor (44) is controlled by the output of the CMOS inverter (22).
Claim 15
Dependent Claim
24 words
The nonvolatile semiconductor memory device according to claim 10, characterized in that the transfer gate (41) is supplied with a word line select signal.
Claim 16
Dependent Claim
35 words
the nonvolatile semiconductor memory device according to claim 1, characterized in that the row decoder circuit (2) permits at least one of the word lines (12) to become a selected condition during the erase mode.
Claim 17
Dependent Claim
35 words
The nonvolatile semiconductor memory device according to claim 1, characterized in that the row decoder circuit (2) permits at least one of the word lines (12) to become an unselected condition during the erase mode.
Claim 18
Dependent Claim
33 words
The nonvolatile semiconductor memory device according to claim 1, characterized in that a read power supply voltage is applied to at least one of source lines (14) of the memory cell transistors (11).
References Cited (Backward Citations)
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