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Patent US5872025A successfully refreshed from Google Patents.
US5872025A
Expired / Lapsed
US
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Method for stacked three dimensional device manufacture
Assignee: International Business Machines Corp
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Filing: 1997-03-11
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Granted: 1999-02-16
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Expires: 2017-03-11
Abstract
Abstract Stacked three-dimensional devices can be prepared by stacking wafers as an alternative to stacking individual devices. Chip regions are formed on several wafers with each chip region being surrounded by a separation region, such as an insulator filled trench. The wafers are then stacked with the chip regions in alignment. Aligning the wafers can be facilitated using notched regions in the periphery of the wafers. The wafers are then joined together by lamination. After laminating the stacks of wafers, stacks of chips are separated by etching, dicing or other processes, which separate out stacked chip devices from the stacked wafer at the chip separation regions. The process allows several stacked chip devices to be manufactured simultaneously.
Inventors
- 👤 John E. Cronin
- 👤 Anthony Palagonia
- 👤 Bernadette A. Pierson
- 👤 Dennis A. Schmidt
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 00:45
CPC Classifications
H; H10; H10W; H10W90/00; H10P; H10P54/00; H10W72/00; H10W72/834; H10W90/20; H10W90/22; H10W90/297; H10W90/701; H10W90/721; H10W90/722; Y; Y10; Y10S; Y10S148/00; Y10S148/028; Y10S438/00; Y10S438/977
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
161 words
A method of forming a plurality of semiconductor chip stacks comprising the steps of: providing a plurality of wafers each having a plurality of chip regions formed therein each of which are surrounded by chip separation regions; joining said plurality of wafers together to form a wafer stack with said chip regions and chip separation regions on said wafers in said wafer stack being in alignment; and then separating a plurality of stacks of chips from said wafer stack, each of said plurality of stacks of chips being comprised of a plurality of chips arranged in a stack, each of said plurality of chips being formed from individual chip regions of said plurality of chip regions in each wafer, said step of separating causing a separation of a stack of chips from said wafer stack at said chip separation regions which are aligned during said joining step wherein said chip separation regions in said wafer are comprised of insulator filled trenches.
Claim 2
Independent Claim
161 words
A method of forming a plurality of semiconductor chip stacks comprising the steps of: providing a plurality of wafers each having a plurality of chip regions formed therein each of which are surrounded by chip separation regions; joining said plurality of wafers together to form a wafer stack with said chip regions and chip separation regions on said wafers in said wafer stack being in alignment; and then separating a plurality of stacks of chips from said wafer stack, each of said plurality of stacks of chips being comprised of a plurality of chips arranged in a stack, each of said plurality of chips being formed from individual chip regions of said plurality of chip regions in each wafer, said step of separating causing a separation of a stack of chips from said wafer stack at said chip separation regions which are aligned during said joining step wherein said chip separation regions in said wafer are comprised of insulator filled trenches.
Claim 3
Dependent Claim
14 words
The method of claim 1 wherein said step of separating is performed by dicing.
Claim 4
Dependent Claim
14 words
The method of claim 1 wherein said step of separating is performed by etching.
Claim 5
Dependent Claim
16 words
The method of claim 1 wherein said step of separating is performed by dicing and etching.
Claim 6
Dependent Claim
14 words
The method of claim 1 wherein said step of joining is performed by laminating.
Claim 7
Dependent Claim
21 words
The method of claim 5 further comprising the step of applying an adhesive to surfaces of said wafers prior to laminating.
Claim 8
Dependent Claim
63 words
The method of claim 1 further comprising the steps of: forming notches in a first wafer of said plurality of wafers; marking said first wafer with a pattern matched to said notches and recording said pattern; marking each of said plurality of wafers with said pattern; and aligning said pattern on each of said plurality of said wafers, prior to said joining step.
Claim 9
Dependent Claim
18 words
The method of claim 7 further comprising the step of forming notches on the periphery of said wafers.
Claim 10
Dependent Claim
53 words
The method of claim 1 further comprising the steps: removing a portion of said wafers from a surface of said wafers whereby said chip separation regions extend from a top to a bottom of said wafers and project above said surface of said wafers; and aligning said chip separation regions on said wafers.
Claim 11
Dependent Claim
23 words
The method of claim 9 further comprising the step of depositing an adhesive on said surface of said wafers after said removing step.
Claim 12
Independent Claim
88 words
A method comprising the steps of: providing a plurality of wafers each having a plurality of circuit areas thereon, each of the wafers having a frontside and a backside, and each of the circuit areas surrounded by an oxide-filled trench; depositing an adhesive onto the backside of at least one of the circuits areas; laminating with the adhesive the plurality of wafers frontside to backside; and separating a stack of the circuit areas formed by the laminating step including removing oxide surrounding the circuit areas in the stack.
Claim 13
Independent Claim
88 words
A method comprising the steps of: providing a plurality of wafers each having a plurality of circuit areas thereon, each of the wafers having a frontside and a backside, and each of the circuit areas surrounded by an oxide-filled trench; depositing an adhesive onto the backside of at least one of the circuits areas; laminating with the adhesive the plurality of wafers frontside to backside; and separating a stack of the circuit areas formed by the laminating step including removing oxide surrounding the circuit areas in the stack.
Claim 14
Dependent Claim
51 words
The method of claim 11 further comprising the step of: forming a plurality of raised oxide rings on the backside of the wafers each coextensive with the oxide-filled trench; and wherein the depositing step includes depositing the adhesive within a perimeter formed by at least one of the raised oxide rings.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-02-15 | 2002-08-17 | 2003-02-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-02-15 | 2006-08-17 | 2007-02-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-02-15 | 2010-08-17 | 2011-02-16 | $7700.00 | Window Closed / Lapsed |