US5867409A
Expired / Lapsed
US
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Linear feedback shift register
Assignee: Toshiba Corp
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Filing: 1997-07-18
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Granted: 1999-02-02
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Expires: 2017-07-18
Abstract
Abstract A linear feedback shift register includes a plurality of groups of flip-flops operated in synchronization with different clock signals and a condition satisfying circuit, provided in a wiring for connecting the pairs of flip-flops to each other, for satisfying conditions for one of linear feedback and generation of pseudorandom numbers.
Inventors
- 👤 Yasuyuki Nozuyama
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 17:43
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/58; G06F7/582; G06F7/584; G06F2207/00; G06F2207/58; G06F2207/581; G06F2207/583
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
80 words
A device for testing an integrated circuit, said device comprising: a plurality of groups of flip-flops forming a linear feedback shift register, each of said groups of flip-flops operated in synchronization with clock signals different from each other in at least one of phase and clock cycle; and a condition satisfying means for connecting said plurality of groups of flip-flops to each other, for satisfying linear feedback conditions for signature compression, and for satisfying conditions for generation of pseudorandom numbers.
Claim 2
Independent Claim
80 words
A device for testing an integrated circuit, said device comprising: a plurality of groups of flip-flops forming a linear feedback shift register, each of said groups of flip-flops operated in synchronization with clock signals different from each other in at least one of phase and clock cycle; and a condition satisfying means for connecting said plurality of groups of flip-flops to each other, for satisfying linear feedback conditions for signature compression, and for satisfying conditions for generation of pseudorandom numbers.
Claim 3
Dependent Claim
56 words
The semiconductor integrated circuit device according to claim 1, wherein said condition satisfying means includes a delay circuit for delaying a signal output from one group of flip-flops to satisfy the linear feedback conditions for signature compression and for satisfying conditions for generation of pseudorandom numbers, and supplying a delayed signal to another group of flip-flops.
Claim 4
Dependent Claim
24 words
The semiconductor integrated device according to claim 2, wherein said delay circuit includes at least one of a flip-flop circuit and a latch circuit.
Claim 5
Independent Claim
96 words
A device for testing a semiconductor integrated circuit, said device comprising: a feedback circuit; a plurality of flip-flops forming a linear feedback shift register operated in synchronization with clock signals different from each other in at least one of phase and clock cycle, wherein said plurality of flip-flops has an input that receives a feedback signal of said feedback circuit and an output that transmits a signal to the feedback circuit; and condition satisfying means provided between at least two of said flip-flops of said plurality of flip-flops for satisfying linear feedback conditions for signature compression.
Claim 6
Independent Claim
96 words
A device for testing a semiconductor integrated circuit, said device comprising: a feedback circuit; a plurality of flip-flops forming a linear feedback shift register operated in synchronization with clock signals different from each other in at least one of phase and clock cycle, wherein said plurality of flip-flops has an input that receives a feedback signal of said feedback circuit and an output that transmits a signal to the feedback circuit; and condition satisfying means provided between at least two of said flip-flops of said plurality of flip-flops for satisfying linear feedback conditions for signature compression.
Claim 7
Dependent Claim
126 words
The semiconductor integrated circuit device according to claim 4, wherein said plurality of flip-flops includes: a first flip-flop supplied with an exclusive OR signal of the feedback signal and a first data signal output from a device-under-test circuit, and operated in synchronization with a first clock signal, a second flip-flop supplied with an exclusive OR signal of an output signal of a preceding flip-flop and a second data signal output from the device-under-test circuit, and operated in synchronization with a second clock signal other than the first clock signal, and said feedback circuit includes an exclusive OR circuit supplied with at least one of an arbitrary output signal of said first flip-flop and an arbitrary output signal of said second flip-flop and generating the feedback signal.
Claim 8
Dependent Claim
16 words
The semiconductor integrated circuit device according to claim 5, further comprising a test result generation circuit.
Claim 9
Dependent Claim
57 words
The semiconductor integrated circuit device according to claim 5, wherein said at least one of the arbitrary output signal of said first flip-flop and the arbitrary output signal of said second flip-flop is input to the exclusive OR circuit of said feedback circuit through said condition satisfying means to satisfy the linear feedback conditions for signature compression.
Claim 10
Dependent Claim
38 words
The semiconductor integrated circuit device according to claim 4, wherein said condition satisfying means includes a delay circuit for delaying an input signal to satisfy the linear feedback conditions for signature compression and for outputting a delayed signal.
Claim 11
Dependent Claim
24 words
The semiconductor integrated circuit device according to claim 8, wherein said delay circuit includes at least one of a flip-flop and a latch circuit.
Claim 12
Dependent Claim
75 words
The semiconductor integrated circuit device according to claim 4, further comprising a clock signal generation circuit for receiving a basic clock signal from outside a chip and generating different clock signals in response to the basic clock signal, said clock signal generation circuit multiplying a frequency of the basic clock signal by a fixed number and generating the different clock signals each having a cycle corresponding to the multiplied frequency as a minimum pulse width.
Claim 13
Dependent Claim
19 words
The semiconductor integrated circuit device according to claim 10, wherein said clock signal generation circuit includes a PLL circuit.
Claim 14
Independent Claim
96 words
A device for testing a semiconductor integrated circuit, said device comprising: a feedback circuit; a plurality of flip-flops forming a linear feedback shift register operated in synchronization with clock signals different from each other in at least one of phase and clock cycle, wherein said plurality of flip-flops has an input that receives a feedback signal of said feedback circuit and an output that transmits a signal to the feedback circuit; and condition satisfying means provided between at least two of said flip-flops of said plurality of flip-flops, for satisfying conditions for generation of pseudorandom numbers.
Claim 15
Independent Claim
96 words
A device for testing a semiconductor integrated circuit, said device comprising: a feedback circuit; a plurality of flip-flops forming a linear feedback shift register operated in synchronization with clock signals different from each other in at least one of phase and clock cycle, wherein said plurality of flip-flops has an input that receives a feedback signal of said feedback circuit and an output that transmits a signal to the feedback circuit; and condition satisfying means provided between at least two of said flip-flops of said plurality of flip-flops, for satisfying conditions for generation of pseudorandom numbers.
Claim 16
Dependent Claim
103 words
The semiconductor integrated circuit device according to claim 12, wherein said plurality of flip-flops includes at least: a first flip-flop group supplied with the feedback signal and operated in synchronization with a first clock signal, a second flip-flop group supplied with an output signal of said first flip-flop group and operated in synchronization with a second clock signal other than the first clock signal, and said feedback circuit includes an exclusive OR circuit supplied with at least one of an arbitrary output signal of said first flip-flop group and an arbitrary output signal of said second flip-flop group and generating the feedback signal.
Claim 17
Dependent Claim
59 words
The semiconductor integrated circuit device according to claim 13, wherein said at least one of the arbitrary output signal of said first flip-flop group and the arbitrary output signal of said second flip-flip group is input to the exclusive OR circuit of said feedback circuit through said condition satisfying means to satisfy the conditions for generation of pseudorandom numbers.
Claim 18
Dependent Claim
16 words
The semiconductor integrated circuit device according to claim 12, further comprising a test data generation circuit.
Claim 19
Dependent Claim
38 words
The semiconductor integrated circuit device according to claim 12, wherein said condition satisfying means includes a delay circuit for delaying an input signal to satisfy the conditions for generation for pseudorandom numbers and for outputting a delayed signal.
Claim 20
Dependent Claim
24 words
The semiconductor integrated circuit device according to claim 16, wherein said delay circuit includes at least one of a flip-flop and a latch circuit.
Claim 21
Dependent Claim
74 words
The semiconductor integrated circuit according to claim 12, further comprising: a clock signal generation circuit for receiving a basic clock signal from outside a chip and generating different clock signals in response to the basic clock signal, said clock signal generation circuit multiplying a frequency of the basic clock signal by a fixed number and generating the different clock signals each having a cycle corresponding to the multiplied frequency as a minimum pulse width.
Claim 22
Dependent Claim
19 words
The semiconductor integrated circuit device according to claim 18, wherein said clock signal generation circuit includes a PLL circuit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-02-01 | 2002-08-03 | 2003-02-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-02-01 | 2006-08-03 | 2007-02-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-02-01 | 2010-08-03 | 2011-02-02 | $7700.00 | Window Closed / Lapsed |