US5090035A
Expired / Lapsed
US
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Linear feedback shift register
Assignee: NEC Corp
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Filing: 1991-01-22
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Granted: 1992-02-18
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Expires: 2011-01-22
Abstract
Abstract A linear feedback shift register comprises a shift register formed of first to (n)th flipflops cascaded in such a manner that an output of a (i)th flipflop is connected to an input of a (i+1)th flipflop, where 2≦n and 1≦i≦(n-1). First to (n)th output terminals are connected to outputs of the first to (n)th flipflops, respectively, and a clock terminal connected to a clock input of each of the flipflops. First to (n-1)th multiplexors of a "1-out-of-2" type are connected at their first input to a common preset value input terminal. Second inputs of the first to (n-1)th multiplexors are connected to the outputs of the first to (n-1)th flipflops, respectively. Each of the first to (n-1)th multiplexors has a control input connected to an individual control terminal. First to (n-1)th exclusive-OR gates are cascaded in such a manner that a first input of a (n-1)th exclusive-OR gate is connected to the output of the (n)th flipflop, a first input of an (i)th exclusive-OR gate is connected to an output of an (i+1)th exclusive-OR gate, and an output of the first exclusive-OR gate is connected to an input of the first flipflop. A second input of the (i)th exclusive-OR gate is connected to an output of the (i)th multiplexor. With this arrangement, a generator polynomial generated by the linear feedback shift register can be modified by controlling the multiplexors through the individual control terminals.
Inventors
- 👤 Makoto Murase
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 14:50
CPC Classifications
G; G11; G11C; G11C19/00; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/31813; G06; G06F; G06F7/00; G06F7/58; G06F7/582; G06F7/584; H; H03; H03K; H03K3/00; H03K3/84; G06F2207/00; G06F2207/58; G06F2207/581; G06F2207/583
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
226 words
A linear feedback shift register comprising a shift register formed of first to (n)th flipflops cascaded in such a manner that an output of a (i)th flipflop is connected to an input of a (i+1)th flipflop, where 2≦n and 1≦i≦(n-1), first to (n)th output terminals connected to outputs of said first to (n)th flipflops, respectively, a clock terminal connected to a clock input of each of said flipflops, first to (n-1)th multiplexors of a "1-out-of-2" type each having a first input connected to a common preset value input terminal, said first to (n-1)th multiplexors having a second input connected to the outputs of said first to (n-1)th flipflops, respectively, to an individual control terminal, and a first set of exclusive-OR gates composed of first to (n-1)th exclusive-OR gates cascaded in such a manner that a first input of a (n-1)th exclusive-OR gate is connected to the output of the (n)th flipflop, a first input of an (i)th exclusive-OR gate is connected to an output of an (i+1)th exclusive-OR gate, and an output of the first exclusive-OR gate is connected to an input of the first flipflop, a second input of the (i)th exclusive-OR gate being connected to an output of the (i)th multiplexor, whereby a generator polynomial generated by the linear feedback shift register can be modified by controlling said multiplexors through said individual control terminals.
Claim 2
Dependent Claim
226 words
A linear feedback shift register comprising a shift register formed of first to (n)th flipflops cascaded in such a manner that an output of a (i)th flipflop is connected to an input of a (i+1)th flipflop, where 2≦n and 1≦i≦(n-1), first to (n)th output terminals connected to outputs of said first to (n)th flipflops, respectively, a clock terminal connected to a clock input of each of said flipflops, first to (n-1)th multiplexors of a "1-out-of-2" type each having a first input connected to a common preset value input terminal, said first to (n-1)th multiplexors having a second input connected to the outputs of said first to (n-1)th flipflops, respectively, to an individual control terminal, and a first set of exclusive-OR gates composed of first to (n-1)th exclusive-OR gates cascaded in such a manner that a first input of a (n-1)th exclusive-OR gate is connected to the output of the (n)th flipflop, a first input of an (i)th exclusive-OR gate is connected to an output of an (i+1)th exclusive-OR gate, and an output of the first exclusive-OR gate is connected to an input of the first flipflop, a second input of the (i)th exclusive-OR gate being connected to an output of the (i)th multiplexor, whereby a generator polynomial generated by the linear feedback shift register can be modified by controlling said multiplexors through said individual control terminals.
Claim 3
Dependent Claim
136 words
A linear feedback shift register claimed in claim 1 further including a second set of exclusive-OR gates composed of first to (n)th exclusive-OR gates arranged in such a manner that an output of an (i)th exclusive-OR gate of said second set of exclusive-OR gates is connected to the input of said (i)th flipflop, and a first input of the (i)th exclusive-OR gate of said second set of exclusive-OR gates is connected to receive an individual input signal, a second input of the first exclusive-OR gate of said second set of exclusive-OR gates being connected to receive the output of said first exclusive-OR gate of said first set of exclusive-OR gates, and a second input of the (i+1)th exclusive-OR gate of said second set of exclusive-OR gates being connected to receive the output of said (i)th flipflop.
Claim 4
Dependent Claim
58 words
A linear feedback shift register claimed in claim 2 wherein said first input of each (i)th exclusive-OR gate of said second set of exclusive-OR gates is connected to an output of a first AND gate having a first input connected to receive said individual input signal and a second input connected in common to a first control terminal.
Claim 5
Dependent Claim
147 words
A linear feedback shift register claimed in claim 3 wherein said second input of each (i)th exclusive-OR gate of said second set of exclusive-OR gates is connected to an output of a second AND gate having a first input connected in common to a second control terminal, said output of the (i)th flipflop being connected to a second input of said second AND gate whose output is connected to said second input of each (i+1)th exclusive-OR gate of said second set of exclusive-OR gates connected to the input of the (i+1)th flipflop, and the second input of said second AND gate whose output is connected to said second input of each first exclusive-OR gate of said second set of exclusive-OR gates connected to the input of the first flipflop being connected to receive the output of said first exclusive-OR gate of said first set of exclusive-OR gates.
Claim 6
Dependent Claim
103 words
A linear feedback shift register claimed in claim 4 wherein the second input of said second AND gate whose output is connected to said second input of each first exclusive-OR gate of said second set of exclusive-OR gates connected to the input of the first flipflop is connected to an output of a second multiplexor having a first input connected to the output of said first exclusive-OR gate of said first set of exclusive-OR gates, a second input of said second multiplexor being connected to a shift input and a control input of said second multiplexor being connected to a third control terminal.
Claim 7
Dependent Claim
74 words
A linear feedback shift register claimed in claim 5 further including an OR gate having first and second inputs connected to said first and second control terminals, respectively, and a third AND gate having a first input connected to an output of said OR gate and a second input connected to said clock terminal, an output of said third AND gate being connected in common to said clock input of each of said flipflop.
Claim 8
Dependent Claim
47 words
A linear feedback shift register claimed in claim 6 further including a second shift register of (n-1) stages having a serial input connected to said shift input, an output of each stage of said second shift register being connected to said control input of a corresponding multiplexor.
Claim 9
Dependent Claim
52 words
A linear feedback shift register claimed in claim 7 wherein said serial input of said second shift register is connected to an output of a fourth AND gate having a first input connected to said clock terminal and a second input connected to the output of said OR gate through an inverter.
References Cited (Backward Citations)
US3736514A
Cited
US4876704A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-02-17 | 1995-08-19 | 1996-02-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-02-17 | 1999-08-19 | 2000-02-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-02-17 | 2003-08-19 | 2004-02-18 | $7700.00 | Window Closed / Lapsed |