US5329254A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor integrated circuit having clock signal generator
Assignee: Sony Corp
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Filing: 1992-08-04
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Granted: 1994-07-12
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Expires: 2012-08-04
Abstract
Abstract A semiconductor integrated circuit having a clock signal generator comprising a ring oscillator, a divider, a phase comparator, and an up-down counter. The ring oscillator provides variable oscillation frequencies determined by a sum of the delay times provided by the circuit elements constituting the oscillator. The divider divides the oscillation frequency from the ring oscillator by a specified number. The phase comparator compares the frequency of the signal from the divider with the frequency of the external clock signal. The up-down counter controls the oscillation frequency of the ring oscillator by selectively operating switches connected with the ring oscillator based on the comparison result from the comparator. The clock generator is controlled by an external clock signal to generate an internal clock signal having a higher frequency and outputs both signals. This makes it possible to constitute the semiconductor integrated circuit by using the digital integrated circuit technology alone, thereby allowing the slow operating semiconductors and fast operating semiconductors to exist on the same circuit without sacrificing the excellent characteristics of the latter.
Inventors
- 👤 Chiaki Takano
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 23:51
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/099; H03L7/0995; H03L7/0997; G; G06; G06F; G06F1/00; G06F1/04; G06F1/08; H03K; H03K3/00; H03K3/02; H03K3/027; H03K3/03; H03K3/0315; H03L7/085; H03L7/089; H03L7/16; H03L7/18; H03L7/183
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
133 words
A semiconductor integrated circuit having a clock signal generator comprising: a ring oscillator having a plurality of selectively operable switches connected in series and a plurality of delay units connected with said switches for providing variable oscillating frequencies determined by a sum of the delay times provided by said delay units; a divider for dividing the oscillation frequency given from said ring oscillator by a specified number; a phase comparator for comparing the frequency of the output signal given from said divider with the frequency of the external clock signal given from the outside; an up-down counter for controlling the oscillation frequency of said ring oscillator by operating said switches, based on the comparison result from said phase comparator; and means for operating said switches in response to operation of said up-down counter.
Claim 2
Dependent Claim
133 words
A semiconductor integrated circuit having a clock signal generator comprising: a ring oscillator having a plurality of selectively operable switches connected in series and a plurality of delay units connected with said switches for providing variable oscillating frequencies determined by a sum of the delay times provided by said delay units; a divider for dividing the oscillation frequency given from said ring oscillator by a specified number; a phase comparator for comparing the frequency of the output signal given from said divider with the frequency of the external clock signal given from the outside; an up-down counter for controlling the oscillation frequency of said ring oscillator by operating said switches, based on the comparison result from said phase comparator; and means for operating said switches in response to operation of said up-down counter.
Claim 3
Dependent Claim
46 words
A semiconductor integrated circuit having a clock signal generator according to claim 1, wherein said semiconductor integrated circuit is composed of both compound semiconductors and Si semiconductors; and means for supplying said compound semiconductors and said Si semiconductors with clock signals from said clock signal generator.
Claim 4
Dependent Claim
172 words
A semiconductor integrated circuit having a clock signal generator comprising: a ring oscillator having a plurality of selectively operable switches connected in series and a plurality of delay units connected with said switches for providing variable oscillating frequencies determined by a sum of the delay times provided by said delay units; a divider for dividing the oscillation frequency given from said ring oscillator by a specified number; a phase comparator for comparing the frequency of the output signal given from said divider with the frequency of an external clock signal given from the outside; an up-down counter for controlling the oscillation frequency of said ring oscillator by operating said switches, based on the comparison result from said phase comparator; and means for operating said switches in response to operation of said up-down counter; wherein said clock signal generator, controlled by said externally entered clock signal to generate an internal clock signal of which frequency is higher than the frequency of said externally entered clock signal, outputs both internal and external clock signals.
Claim 5
Dependent Claim
172 words
A semiconductor integrated circuit having a clock signal generator comprising: a ring oscillator having a plurality of selectively operable switches connected in series and a plurality of delay units connected with said switches for providing variable oscillating frequencies determined by a sum of the delay times provided by said delay units; a divider for dividing the oscillation frequency given from said ring oscillator by a specified number; a phase comparator for comparing the frequency of the output signal given from said divider with the frequency of an external clock signal given from the outside; an up-down counter for controlling the oscillation frequency of said ring oscillator by operating said switches, based on the comparison result from said phase comparator; and means for operating said switches in response to operation of said up-down counter; wherein said clock signal generator, controlled by said externally entered clock signal to generate an internal clock signal of which frequency is higher than the frequency of said externally entered clock signal, outputs both internal and external clock signals.
Claim 6
Dependent Claim
173 words
A semiconductor integrated circuit having a clock signal generator comprising: a ring oscillator having a plurality of selectively operable switches connected in series and a plurality of delay units connected with said switches for providing variable oscillating frequencies determined by a sum of the delay times provided by said delay units; a divider for dividing the oscillation frequency given from said ring oscillator by a specified number; a phase comparator for comparing the frequency of the output signal given from said divider with the frequency of an external clock signal given from the outside; an up-down counter for controlling the oscillation frequency of said ring oscillator by operating said switches, based on the comparison result from said phase comparator; and means for operating said switches in response to operation of said up-down counter; wherein said clock signal generator generates an internal clock signal having a frequency which is higher than the frequency of said externally entered clock signal to operate the circuit elements internal to said clock signal generator at a high speed.
Claim 7
Dependent Claim
173 words
A semiconductor integrated circuit having a clock signal generator comprising: a ring oscillator having a plurality of selectively operable switches connected in series and a plurality of delay units connected with said switches for providing variable oscillating frequencies determined by a sum of the delay times provided by said delay units; a divider for dividing the oscillation frequency given from said ring oscillator by a specified number; a phase comparator for comparing the frequency of the output signal given from said divider with the frequency of an external clock signal given from the outside; an up-down counter for controlling the oscillation frequency of said ring oscillator by operating said switches, based on the comparison result from said phase comparator; and means for operating said switches in response to operation of said up-down counter; wherein said clock signal generator generates an internal clock signal having a frequency which is higher than the frequency of said externally entered clock signal to operate the circuit elements internal to said clock signal generator at a high speed.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1997-07-11 | 1998-01-10 | 1998-07-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-07-11 | 2002-01-10 | 2002-07-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-07-11 | 2006-01-10 | 2006-07-12 | $7700.00 | Window Closed / Lapsed |