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US5862371A
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Method and system for instruction trace reconstruction utilizing performance monitor outputs and bus monitoring
Assignee: International Business Machines Corp
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Filing: 1996-11-25
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Granted: 1999-01-19
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Expires: 2016-11-25
Abstract
Abstract A method and system for instruction trace reconstruction utilizing performance monitor outputs and bus monitoring. Performance projections for processor systems and memory subsystems are important for a correct understanding of work loads within the system. An instruction trace is generally utilized to determine distribution of instructions, identification of register dependencies, branch path analyzes and timing. One well known technique for reconstructing an instruction trace can be accomplished by monitoring bus traffic to determine instruction addresses, data addresses and data during the trace, if the initial architectural state of the system is known. The difficulty in reconstructing an instruction trace from monitored bus traffic can be decreased substantially if more definitive information regarding the actual instruction sequence can be obtained. To this end, an internal performance monitor within the processor system is utilized to generate an output each processor clock cycle which is indicative of the exact number of instructions which were executed during that clock cycle, an indication of whether or not a branch instruction was taken or not taken, an offset for each interrupt vector which has been taken, the number of data cache misses, the number of instruction cache misses, the number of store conditional instructions which were executed and the number of store conditional instructions which failed. This information, in combination with monitored bus traffic may be utilized to efficiently and accurately reconstruct an instruction trace without adversely affecting performance of the system under test.
Inventors
- 👤 Frank Eliot Levine
- 👤 William John Starke
- 👤 Edward Hugh Welbon
- 👤 Jack Chris Randolph
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 13:37
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/36; G06F11/362; G06F11/3636; G06F11/30; G06F11/34; G06F11/3466; G06F11/349; G06F2201/00; G06F2201/885
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
139 words
A method of tracing the execution of a plurality of instructions within a processor system which includes a processor, a main memory, a processor clock and a cache memory, which are interconnected via a bus, said method comprising the steps of: executing a series of instructions; initiating an instruction trace; in response to said initiation of said instruction trace, determining an initial state of said cache memory and monitoring subsequent instruction addresses, data addresses and data on said bus; during each processor clock cycle, detecting an exact number of instructions executed, an indication of whether each branch instruction is taken or not taken, and providing an output in response to each such detection; and thereafter, reconstructing an instruction trace utilizing said monitor to instruction addresses, data addresses and data, said initial state of said cache memory and said outputs.
Claim 2
Independent Claim
139 words
A method of tracing the execution of a plurality of instructions within a processor system which includes a processor, a main memory, a processor clock and a cache memory, which are interconnected via a bus, said method comprising the steps of: executing a series of instructions; initiating an instruction trace; in response to said initiation of said instruction trace, determining an initial state of said cache memory and monitoring subsequent instruction addresses, data addresses and data on said bus; during each processor clock cycle, detecting an exact number of instructions executed, an indication of whether each branch instruction is taken or not taken, and providing an output in response to each such detection; and thereafter, reconstructing an instruction trace utilizing said monitor to instruction addresses, data addresses and data, said initial state of said cache memory and said outputs.
Claim 3
Dependent Claim
47 words
The method of tracing the execution of a plurality of instructions within a processor system according to claim 1, further including the step of: during each processor clock cycle, detecting an offset value for each interrupt vector taken and providing an output in response to said detection.
Claim 4
Dependent Claim
44 words
The method of tracing the execution of a plurality of instructions within a processor system according to claim 1, further including the step of: during each processor clock cycle, detecting each store conditional instruction executed and providing an output in response to said detection.
Claim 5
Dependent Claim
45 words
The method of tracing the execution of a plurality of instructions within a processor system according to claim 1, further including the step of: during each processor clock cycle, detecting each store conditional instruction which fails and providing an output in response to said detection.
Claim 6
Dependent Claim
64 words
The method of tracing the execution of a plurality of instructions within a processor system according to claim 1, wherein said processor system further includes a plurality of registers and buffers and wherein said method further includes the step of: copying the content of at least selected ones of said plurality of buffers and registers in response to said initiation of said instruction trace.
Claim 7
Dependent Claim
41 words
The system for tracing the execution of a plurality of instructions within a processor system according to claim 1, further including: means for detecting an offset value for each interrupt vector taken and providing an output in response to said detection.
Claim 8
Dependent Claim
38 words
The system for tracing the execution of a plurality of instructions within a processor system according to claim 1, further including: means for detecting each store conditional instruction executed and providing an output in response to said detection.
Claim 9
Dependent Claim
39 words
The system for tracing the execution of a plurality of instructions within a processor system according to claim 1, further including: means for detecting each store conditional instruction which fails and providing an output in response to said detection.
Claim 10
Dependent Claim
63 words
The system for tracing the execution of a plurality of instructions within a processor system according to claim 1, wherein said processor system further includes a plurality of registers and buffers and wherein said system further includes: means for copying the content of at least selected ones of said plurality of buffers and registers in response to said initiation of said instruction trace.
Claim 11
Independent Claim
140 words
A system for tracing the execution of a plurality of instructions within a processor system which includes a processor, a main memory, a processor clock and a cache memory, which are interconnected via bus, said system comprising: means for executing a series of instructions; means for initiating an instruction trace; means for determining an initial state of said cache memory and monitoring subsequent instruction addresses, data addresses and data on said bus in response to said initiation of said instruction trace; means for detecting an exact number of instructions executed, an indication of whether each branch instruction is taken or not taken, and providing an output in response to each such detection; and means for thereafter reconstructing an instruction trace utilizing said monitor to instruction addresses, data addresses and data, said initial state of said cache memory and said outputs.
Claim 12
Independent Claim
140 words
A system for tracing the execution of a plurality of instructions within a processor system which includes a processor, a main memory, a processor clock and a cache memory, which are interconnected via bus, said system comprising: means for executing a series of instructions; means for initiating an instruction trace; means for determining an initial state of said cache memory and monitoring subsequent instruction addresses, data addresses and data on said bus in response to said initiation of said instruction trace; means for detecting an exact number of instructions executed, an indication of whether each branch instruction is taken or not taken, and providing an output in response to each such detection; and means for thereafter reconstructing an instruction trace utilizing said monitor to instruction addresses, data addresses and data, said initial state of said cache memory and said outputs.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-01-18 | 2002-07-20 | 2003-01-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-01-18 | 2006-07-20 | 2007-01-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-01-18 | 2010-07-20 | 2011-01-19 | $7700.00 | Window Closed / Lapsed |