US5742804A
Expired / Lapsed
US
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Instruction prefetch mechanism utilizing a branch predict instruction
Assignee: Institute for Development of Emerging Architectures LLC
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Filing: 1996-07-24
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Granted: 1998-04-21
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Expires: 2016-07-24
Abstract
Abstract A processor and method that reduces instruction fetch penalty in the execution of a program sequence of instructions comprises a branch predict instruction that is inserted into the program at a location which precedes the branch. The branch predict instruction has an opcode that specifies a branch as likely to be taken or not taken, and which also specifies a target address of the branch. A block of target instructions, starting at the target address, is prefetched into the instruction cache of the processor so that the instructions are available for execution prior to the point in the program where the branch is encountered. Also specified by the opcode is an indication of the size of the block of target instructions, and a trace vector of a path in the program sequence that leads to the target from the branch predict instruction for better utilization of limited memory bandwidth.
Inventors
- 👤 Tse-Yu Yeh
- 👤 Mircea Poplingher
- 👤 Kent G. Fielden
- 👤 Hans Mulder
- 👤 Rajiv Gupta
- 👤 Dale Morris
- 👤 Michael Schlansker
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 08:39
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3802; G06F9/3804; G06F9/3836; G06F9/3842; G06F9/3846; G06F9/3854
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
136 words
A method of reducing instruction fetch penalty in the execution of a programmed sequence of instructions which includes branches, the method comprising the steps of: (a) inserting at a location in the programmed sequence a branch predict instruction having an opcode that specifies a branch as taken or not taken, and a target address of the branch, and a trace vector of a path in the programmed sequence that leads to the target address from the branch predict instruction, the branch predict instruction otherwise not affecting an architectural state of the microprocessor, and wherein the location precedes the branch by a predetermined number of instructions; (b) prefetching a block of target instructions, starting at the target address of the branch, into an instruction cache of the microprocessor before the branch is encountered in the programmed sequence.
Claim 2
Independent Claim
136 words
A method of reducing instruction fetch penalty in the execution of a programmed sequence of instructions which includes branches, the method comprising the steps of: (a) inserting at a location in the programmed sequence a branch predict instruction having an opcode that specifies a branch as taken or not taken, and a target address of the branch, and a trace vector of a path in the programmed sequence that leads to the target address from the branch predict instruction, the branch predict instruction otherwise not affecting an architectural state of the microprocessor, and wherein the location precedes the branch by a predetermined number of instructions; (b) prefetching a block of target instructions, starting at the target address of the branch, into an instruction cache of the microprocessor before the branch is encountered in the programmed sequence.
Claim 3
Dependent Claim
19 words
The method according to claim 1 wherein the opcode further specifies a size of the block of target instructions.
Claim 4
Dependent Claim
23 words
The method according to claim 2 wherein the size is specified as large if the block target instruction is greater than 32 bytes.
Claim 5
Dependent Claim
23 words
The method according to claim 2 wherein the size is specified as large if the block target instruction is greater than 64 bytes.
Claim 6
Dependent Claim
39 words
The method according to claim 2 further comprising the step of: repeating step (b) in a streaming operation that sequentially prefetches instructions of the block of target instructions when the size is greater than a predetermined number of bytes.
Claim 7
Dependent Claim
32 words
The method according to claim 1 further comprising the step of: eliminating a prefetch request of a second branch predict instruction based upon a trace vector of the second branch predict instruction.
Claim 8
Dependent Claim
60 words
The method according to claim 6 wherein the eliminating step comprises the steps of: predicting an execution path of the programmed sequence of instructions; comparing the execution path with the trace vector of the second branch predict instruction; and canceling the prefetch request if the execution path and the trace vector of the second branch predict instruction do not match.
Claim 9
Dependent Claim
24 words
The method according to claim 1 further comprising the step of: generating the trace vector by a compiler of the programmed sequence of instructions.
Claim 10
Dependent Claim
23 words
The method according to claim 8 wherein the trace vector comprises a bit field that encodes two or more levels of the path.
Claim 11
Dependent Claim
119 words
A microprocessor for executing a programmed set of instructions that includes a branch, the microprocessor comprising: a decoder that decodes a branch predict instruction located within the programmed sequence a predetermined number of instructions prior to the branch, the branch predict instruction having an opcode field that specifies the branch as taken or not taken, a target address of the branch, and a trace vector of a path in the programmed sequence that leads to the target address from the branch predict instruction, execution of the branch predict instruction otherwise not affecting an architectural state of the microprocessor; and a prefetching mechanism that prefetches a target block of instructions at a target address responsive to the branch predict instruction.
Claim 12
Dependent Claim
119 words
A microprocessor for executing a programmed set of instructions that includes a branch, the microprocessor comprising: a decoder that decodes a branch predict instruction located within the programmed sequence a predetermined number of instructions prior to the branch, the branch predict instruction having an opcode field that specifies the branch as taken or not taken, a target address of the branch, and a trace vector of a path in the programmed sequence that leads to the target address from the branch predict instruction, execution of the branch predict instruction otherwise not affecting an architectural state of the microprocessor; and a prefetching mechanism that prefetches a target block of instructions at a target address responsive to the branch predict instruction.
Claim 13
Dependent Claim
18 words
The microprocessor of claim 10 wherein the opcode further specifies a size of the target block of instructions.
Claim 14
Dependent Claim
22 words
The microprocessor of claim 10 wherein the trace vector comprises a bit field that encodes two or more levels of the path.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-04-20 | 2001-10-20 | 2002-04-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-04-20 | 2005-10-20 | 2006-04-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-04-20 | 2009-10-20 | 2010-04-21 | $7700.00 | Window Closed / Lapsed |