US5861647A
Expired / Lapsed
US
⏱️ 0.0 years remaining
VLSI capacitors and high Q VLSI inductors using metal-filled via plugs
Assignee: National Semiconductor Corp
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Filing: 1996-10-02
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Granted: 1999-01-19
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Expires: 2016-10-02
Abstract
Abstract Disclosed are methods of making inductors and capacitors, comprising filling a via in a dielectric disposed between two metal layers with a metal plug. The plug comprises tungsten, aluminum or copper and extends the length of the metal layers. The plug connects the two metal layers to form the inductor. Two plugs can be formed so as to connect the two metal layers so as to form a parallel plate capacitor.
Inventors
- 👤 Ji Zhao
- 👤 Chih Sieh Teng
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 11:23
CPC Classifications
H; H10; H10D; H10D1/00; H10D1/20; H10D1/60; H10D1/68; H10W; H10W20/00; H10W20/40; H10W20/495; H10W20/496; H10W20/497
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
128 words
A parallel plate capacitor formed between first and second spaced apart etched metal layers on an integrated circuit device in which said first etched layer includes a longitudinal segment having a length greater than its width, said plates of said capacitor comprising: first and second spaced apart etched metal layers separated by a dielectric layer; first and second metal-filled via plugs spaced apart from each other, extending through said dielectric layer and shunting together said first and second spaced apart etched metal layers, wherein the longitudinal axis of said plugs is perpendicular to said segment, each of said plugs has a length that is substantially the same as the length of said segment and said plugs are separated from each other by a portion of said dielectric layer.
Claim 2
Dependent Claim
128 words
A parallel plate capacitor formed between first and second spaced apart etched metal layers on an integrated circuit device in which said first etched layer includes a longitudinal segment having a length greater than its width, said plates of said capacitor comprising: first and second spaced apart etched metal layers separated by a dielectric layer; first and second metal-filled via plugs spaced apart from each other, extending through said dielectric layer and shunting together said first and second spaced apart etched metal layers, wherein the longitudinal axis of said plugs is perpendicular to said segment, each of said plugs has a length that is substantially the same as the length of said segment and said plugs are separated from each other by a portion of said dielectric layer.
Claim 3
Dependent Claim
16 words
A parallel plate capacitor according to claim 1, wherein said plugs comprise tungsten, aluminum or copper.
Claim 4
Dependent Claim
81 words
A high Q inductor formed on an integrated circuit device, said inductor comprising: first and second spaced apart etched metal layers separated by a dielectric layer; and a metal plug shunting together said first and second spaced apart etched metal layers extending through said dielectric and having a longitudinal axis perpendicular to the plane of said device, a length greater than its width and said length of said plug is substantially the same as the length of said first etched layer.
Claim 5
Dependent Claim
81 words
A high Q inductor formed on an integrated circuit device, said inductor comprising: first and second spaced apart etched metal layers separated by a dielectric layer; and a metal plug shunting together said first and second spaced apart etched metal layers extending through said dielectric and having a longitudinal axis perpendicular to the plane of said device, a length greater than its width and said length of said plug is substantially the same as the length of said first etched layer.
Claim 6
Dependent Claim
16 words
An article of manufacture according to claim 3, wherein said plug comprises tungsten, aluminum or copper.
Claim 7
Dependent Claim
67 words
A high Q inductor on an integrated circuit device, said inductor comprising: a metal plug in a via formed in a dielectric layer, wherein said dielectric layer separates first and second spaced apart etched metal layers and said metal plug shunts together said first and second spaced apart etched metal layers; and said first and second spaced apart etched metal layers between which said metal plug extends.
Claim 8
Dependent Claim
67 words
A high Q inductor on an integrated circuit device, said inductor comprising: a metal plug in a via formed in a dielectric layer, wherein said dielectric layer separates first and second spaced apart etched metal layers and said metal plug shunts together said first and second spaced apart etched metal layers; and said first and second spaced apart etched metal layers between which said metal plug extends.
Claim 9
Dependent Claim
30 words
A high Q inductor according to claim 5, wherein said plug comprises a metal that is different than the metal in said first and second spaced apart etched metal layers.
Claim 10
Dependent Claim
114 words
A parallel plate capacitor on an integrated circuit device, said capacitor comprising: first and second plates parallel to each other and perpendicular to the plane of said device, wherein each of said plates includes first and second spaced apart etched metal layers shunted together by a metal plug, the plane of each of said first and second spaced apart etched metal layers is parallel to the plane of said device and said metal plug is in a via formed in a dielectric layer separating said first and second spaced apart etched metal layers and the axis of said plug is parallel to said plane of said first and second spaced apart etched metal layers.
Claim 11
Dependent Claim
114 words
A parallel plate capacitor on an integrated circuit device, said capacitor comprising: first and second plates parallel to each other and perpendicular to the plane of said device, wherein each of said plates includes first and second spaced apart etched metal layers shunted together by a metal plug, the plane of each of said first and second spaced apart etched metal layers is parallel to the plane of said device and said metal plug is in a via formed in a dielectric layer separating said first and second spaced apart etched metal layers and the axis of said plug is parallel to said plane of said first and second spaced apart etched metal layers.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-01-18 | 2002-07-20 | 2003-01-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-01-18 | 2006-07-20 | 2007-01-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-01-18 | 2010-07-20 | 2011-01-19 | $7700.00 | Window Closed / Lapsed |