Patent US5858816A successfully refreshed from Google Patents.
US5858816A
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US
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Method for producing circuit board, for semiconductor package, having cavity for accommodating semiconductor element
Assignee: Shinko Electric Industries Co Ltd
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Filing: 1997-12-16
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Granted: 1999-01-12
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Expires: 2017-12-16
Abstract
Abstract In a method for producing a circuit board for a semiconductor package, portions of the resist film formed on the respective surface of the core substrate are removed during the exposure/development process, which portions correspond to the circuit pattern and to the cavity opening but having a diameter smaller than that of the cavity opening, whereby the photosensitive portion of the resist film is hardened while extending inward from the upper edge of the cavity opening to a predetermined distance. The resist film operates as a resist for the conductor layer to be formed on the inner wall of the cavity opening and connected to the circuit pattern on one surface of the core substrate. Thereby, since the finally formed conductor layer does not reach the upper edge of the cavity opening at a predetermined vacant space therefrom, short-circuiting of the signal line is prevented from occurring even if the bonding wire is brought into contact with the upper edge of the cavity opening. Thus, it is possible to improve the yield in the production of plastic packages as well as the quality of the resultant packages.
Inventors
- 👤 Hiroaki Sato
- 👤 Masayoshi Ebe
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 15:35
CPC Classifications
H; H10; H10W; H10W72/00; H10W72/071; H10W70/00; H10W70/60; H10W70/62; H10W70/65; H10W70/657; H05; H05K; H05K3/00; H05K3/40; H05K3/42; H05K3/425; H05K3/427; H10W70/01; H10W70/05; H10W99/00; H05K2201/00; H05K2201/09; H05K2201/09209; H05K2201/095; H05K2201/09545; H05K2201/09581; H05K3/0094; H05K3/10; H05K3/108; H10W70/67; H10W70/68; H10W70/682; H10W70/685; H10W72/50; H10W72/541; H10W72/5449; H10W90/00; H10W90/701; H10W90/751; H10W90/754
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
226 words
A method for producing a circuit board for a semiconductor package, comprising the steps of: forming an opening for a cavity for accommodating a semiconductor element at a predetermined portion of a core substrate having metallic layers on both surfaces thereof, forming a first plating film on the inner wall of the cavity opening to be connected to a circuit pattern formed on at least one surface of the core substrate, forming a resist film on both the surfaces of the core substrate so that the cavity opening is covered, removing a portion of the resist film corresponding to the circuit pattern on the core substrate and a portion thereof corresponding to the cavity opening but having a diameter smaller than that of the cavity opening by an exposure/development process, forming a second plating film while using the resist film as a mask, on a portion corresponding to the circuit pattern exposed on the core substrate and the first plating film formed on the inner wall of the cavity opening, releasing the resist film from both the surfaces of the core substrate, removing a portion of the first plating film exposed on the core substrate and the underlying metallic layer, and removing the second plating film covering the portion corresponding to the circuit pattern of the core substrate and the inner wall of the cavity opening.
Claim 2
Independent Claim
226 words
A method for producing a circuit board for a semiconductor package, comprising the steps of: forming an opening for a cavity for accommodating a semiconductor element at a predetermined portion of a core substrate having metallic layers on both surfaces thereof, forming a first plating film on the inner wall of the cavity opening to be connected to a circuit pattern formed on at least one surface of the core substrate, forming a resist film on both the surfaces of the core substrate so that the cavity opening is covered, removing a portion of the resist film corresponding to the circuit pattern on the core substrate and a portion thereof corresponding to the cavity opening but having a diameter smaller than that of the cavity opening by an exposure/development process, forming a second plating film while using the resist film as a mask, on a portion corresponding to the circuit pattern exposed on the core substrate and the first plating film formed on the inner wall of the cavity opening, releasing the resist film from both the surfaces of the core substrate, removing a portion of the first plating film exposed on the core substrate and the underlying metallic layer, and removing the second plating film covering the portion corresponding to the circuit pattern of the core substrate and the inner wall of the cavity opening.
Claim 3
Dependent Claim
48 words
A method for producing a circuit board for a semiconductor package as defined by claim 1, wherein the step for forming the first plating film is carried out by applying an electroless plating of copper or copper alloy and subsequently applying an electro-plating of copper or copper alloy.
Claim 4
Dependent Claim
50 words
A method for producing a circuit board for a semiconductor package as defined by claim 1, wherein the step of forming the first plating film is carried out by adhering palladium cores on the inner wall of the cavity opening and subsequently applying an electro-plating of copper or copper alloy.
Claim 5
Dependent Claim
45 words
A method for producing a circuit board for a semiconductor package as defined by claim 1, wherein an electro-plating of copper or copper alloy is applied to the portion corresponding to the circuit pattern carrying the first plating film prior to applying the second plating.
Claim 6
Dependent Claim
71 words
A method for producing a circuit board for a semiconductor package as defined by claim 1, wherein a photosensitive film is used as the resist film in the exposure/development process, and a photo-mask overlaid on the photosensitive film is adapted so that a photosensitive area of the photosensitive film extends into the cavity opening from the upper edge of the inner wall of the cavity opening by at least 40 μm.
Claim 7
Dependent Claim
34 words
A method for producing a circuit board for a semiconductor package as defined by claim 5, wherein the step for releasing the photosensitive film is carried out by swelling the photosensitive film with water.
Claim 8
Dependent Claim
35 words
A method for producing a circuit board for a semiconductor package as defined by claim 1, wherein the step for applying the second plating film is carried out by an electro-plating of tin or solder.
Claim 9
Dependent Claim
54 words
A method for producing a circuit board for a semiconductor package as defined by claim 1, wherein a step is added after the step for removing the second plating film, for adhering a heat radiation plate to one surface of the core substrate to close the cavity opening so that the cavity is defined.
Claim 10
Dependent Claim
36 words
A method for producing a circuit board for a semiconductor package as defined by claim 8, wherein the heat radiation plate is adhered to the one surface of the core substrate via resinous adhesive or solder.
Claim 11
Dependent Claim
46 words
A method for producing a circuit board for a semiconductor package as defined by claim 8, wherein a step is added for forming a multi-layer structure by overlaying a circuit board having a cavity opening of different area onto the other surface of the circuit board.
Claim 12
Dependent Claim
47 words
A method for producing a circuit board for a semiconductor package as defined by claim 8, wherein a step is added, after the step for removing the second plating film, for defining the cavity by adhering a circuit board on the one surface of the core substrate.
References Cited (Backward Citations)
US4965227A
Cited
US5205036A
Cited
JPH0432252A
Cited
US5556807A
Cited
US5441918A
Cited
US5474957A
Cited
US5607883A
Cited
US5599747A
Cited
US5557502A
Cited
US5643818A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-01-11 | 2002-07-13 | 2003-01-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-01-11 | 2006-07-13 | 2007-01-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-01-11 | 2010-07-13 | 2011-01-12 | $7700.00 | Window Closed / Lapsed |