Patent US5856221A successfully refreshed from Google Patents.
US5856221A
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Process for forming an integrated circuit comprising non-volatile memory cells and side transistors of at least two different types, and corresponding IC
Assignee: STMicroelectronics SRL
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Filing: 1996-06-20
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Granted: 1999-01-05
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Expires: 2016-06-20
Abstract
Abstract A process or forming an integrated circuit calls for the provision of at least one matrix of non-volatile memory cells including an intermediate dielectric multilayer comprising a lower silicon oxide layer, an intermediate silicon nitride layer and an upper silicon oxide layer. The process calls for the simultaneous provision in zones peripheral to the memory cells of at least one first and one second transistor type each having a gate dielectric of a first and a second thickness respectively. After formation of the floating gate of the cells with a gate oxide layer and a polycrystalline silicon layer and the formation of the lower silicon oxide layer and of the intermediate silicon nitride layer, the process in accordance with the present invention includes removal of said layers from the zones peripheral to the matrix, and formation of a first silicon oxide layer over the substrate in the areas of both types of transistor. The process further includes removal of the preceding layer from areas assigned only to the transistors of the second type; deposition of said upper silicon oxide layer over the memory cells, over the first silicon oxide layer in the areas of the transistors of the first type and over the substrate in the areas of the transistors of the second type; and formation of a second silicon oxide layer in the areas of both types of peripheral transistors.
Inventors
- 👤 Cesare Clementi
- 👤 Gabriella Ghidini
- 👤 Carlo Riva
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 20:56
CPC Classifications
H; H10; H10B; H10B41/00; H10B41/40; H10B41/42; H10B41/49
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
311 words
A process for forming an integrated circuit in a monocrystalline silicon substrate having implemented thereon a matrix of non-volatile memory cells each having a floating gate and a control gate, each floating gate and control gate being electroconductive and insulated electrically from each other by means of an intermediate dielectric multilayer having a lower silicon oxide layer, an intermediate silicon nitride layer, and an upper silicon oxide layer and the substrate also having simultaneous implementation, in peripheral zones of the memory cells, at least first and second transistors having a gate dielectric of a first and second thickness respectively, the process comprising the steps of: (A) forming a gate oxide layer, a polycrystalline silicon layer, the lower silicon oxide layer, and the intermediate silicon nitride layer; (B) removal of the lower silicon oxide layer, the intermediate silicon nitride layer, the polycrystalline silicon layer, and the gate oxide layer from the peripheral zones; (C) formation of a first silicon oxide layer over the substrate in the areas of the first and the second transistors; (D) removal of the first silicon oxide layer from the areas of the substrate including only the second transistor; (E) after step (D), simultaneous deposition of a silicon oxide layer over the memory cells and the peripheral zones in which the at least first and second transistors are formed, the silicon oxide layer forming the upper silicon oxide layer of the intermediate dielectric multilayer of the memory cells, and at least part of the gate dielectrics of the first and second transistors, the silicon oxide layer being deposited over the first silicon oxide layer in the areas including the first transistor, and over the substrate in the areas including the second transistor; and (F) formation of a second silicon oxide layer in the areas of the substrate including the transistors of both the first and the second transistors.
Claim 2
Dependent Claim
311 words
A process for forming an integrated circuit in a monocrystalline silicon substrate having implemented thereon a matrix of non-volatile memory cells each having a floating gate and a control gate, each floating gate and control gate being electroconductive and insulated electrically from each other by means of an intermediate dielectric multilayer having a lower silicon oxide layer, an intermediate silicon nitride layer, and an upper silicon oxide layer and the substrate also having simultaneous implementation, in peripheral zones of the memory cells, at least first and second transistors having a gate dielectric of a first and second thickness respectively, the process comprising the steps of: (A) forming a gate oxide layer, a polycrystalline silicon layer, the lower silicon oxide layer, and the intermediate silicon nitride layer; (B) removal of the lower silicon oxide layer, the intermediate silicon nitride layer, the polycrystalline silicon layer, and the gate oxide layer from the peripheral zones; (C) formation of a first silicon oxide layer over the substrate in the areas of the first and the second transistors; (D) removal of the first silicon oxide layer from the areas of the substrate including only the second transistor; (E) after step (D), simultaneous deposition of a silicon oxide layer over the memory cells and the peripheral zones in which the at least first and second transistors are formed, the silicon oxide layer forming the upper silicon oxide layer of the intermediate dielectric multilayer of the memory cells, and at least part of the gate dielectrics of the first and second transistors, the silicon oxide layer being deposited over the first silicon oxide layer in the areas including the first transistor, and over the substrate in the areas including the second transistor; and (F) formation of a second silicon oxide layer in the areas of the substrate including the transistors of both the first and the second transistors.
Claim 3
Dependent Claim
27 words
The process of claim 1, wherein step (F) includes forming the second silicon oxide layer with oxidation by a treatment of the substrate in an oxidizing ambient.
Claim 4
Dependent Claim
41 words
The process of claim 2, wherein the oxidizing ambient is at a temperature between 750° C. and 950° C. in an atmosphere containing at least one of the following compounds from the group consisting of O 2 and H 2 O.
Claim 5
Dependent Claim
20 words
The process of claim 1, wherein step (C) includes forming the first silicon oxide layer with oxidation of the substrate.
Claim 6
Dependent Claim
43 words
The process of claim 4, wherein the step of oxidation is performed at a temperature between 750° C. and 950° C. in an atmosphere containing at least one of the following compounds from the group consisting of O 2 and H 2 O.
Claim 7
Dependent Claim
17 words
The process of claim 1, further comprising a step of nitridizing of the second silicon oxide layer.
Claim 8
Dependent Claim
74 words
The process of claim 1, wherein step (D) includes a first step of partial removal of the first silicon oxide layer from the areas of the substrate including only the second transistor, and a second step of removal from portions of the substrate not subjected to the first removal step, the second step performed until the first silicon oxide layer is completely removed from the areas of the substrate including only the second transistor.
Claim 9
Dependent Claim
16 words
The process of claim 1, wherein the at least first and second transistors are CMOS transistors.
Claim 10
Dependent Claim
41 words
The process of claim 1, wherein the thickness of said upper deposited silicon oxide layer is between 50 Å and 250 Å and said first and said second thicknesses of the gate dielectric are between 70 Å and 350 Å, respectively.
Claim 11
Independent Claim
245 words
A method of fabricating an integrated circuit formed on a substrate, the integrated circuit including a memory cell and first and second transistors, the memory cell including a floating gate, a control gate, and a multilayer dielectric for insulating the floating gate from the control gate, and the first and second transistors including first and second multilayer gate dielectrics having first and second thicknesses, respectively, the method comprising the steps of: (A) removal of layers forming the memory cell from an area of the substrate in which the first and second transistors are to be formed, the area being peripheral to an area of the substrate in which the memory cell is formed; (B) forming a first dielectric layer in the area of the substrate in which the first and second transistors are formed; (C) removing the first dielectric layer from an area of the substrate in which only the first transistor is formed; (D) after step (C), simultaneously forming a second dielectric over the memory cell and the areas of the substrate in which the first and second transistors are formed, the second dielectric forming part of the multilayer dielectric of the memory cell, and part of the first and second multilayer gate dielectrics of the first and second transistors, respectively; and (E) forming a third dielectric layer in the area of the substrate in which the first and second transistors are formed, such that the second thickness is greater than the first thickness.
Claim 12
Independent Claim
245 words
A method of fabricating an integrated circuit formed on a substrate, the integrated circuit including a memory cell and first and second transistors, the memory cell including a floating gate, a control gate, and a multilayer dielectric for insulating the floating gate from the control gate, and the first and second transistors including first and second multilayer gate dielectrics having first and second thicknesses, respectively, the method comprising the steps of: (A) removal of layers forming the memory cell from an area of the substrate in which the first and second transistors are to be formed, the area being peripheral to an area of the substrate in which the memory cell is formed; (B) forming a first dielectric layer in the area of the substrate in which the first and second transistors are formed; (C) removing the first dielectric layer from an area of the substrate in which only the first transistor is formed; (D) after step (C), simultaneously forming a second dielectric over the memory cell and the areas of the substrate in which the first and second transistors are formed, the second dielectric forming part of the multilayer dielectric of the memory cell, and part of the first and second multilayer gate dielectrics of the first and second transistors, respectively; and (E) forming a third dielectric layer in the area of the substrate in which the first and second transistors are formed, such that the second thickness is greater than the first thickness.
Claim 13
Dependent Claim
27 words
The method of claim 10, wherein step (A) includes the steps of photolithographic masking of the substrate and chemical etching of the layers forming the memory cell.
Claim 14
Dependent Claim
13 words
The method of claim 11, wherein step (B) includes oxidation of the substrate.
Claim 15
Dependent Claim
23 words
The method of claim 12, wherein step (C) includes photolithographic masking of the substrate and chemical etching of the the first dielectric layer.
Claim 16
Dependent Claim
31 words
The method of claim 13, wherein step (D) includes depositing silicon oxide over the memory cell and the areas of the substrate in which the first and second transistors are formed.
Claim 17
Independent Claim
12 words
The method of claim wherein step (E) includes oxidation of the substrate.
Claim 18
Dependent Claim
41 words
The method of claim 1, wherein the at least first and second transistors include a plurality of first transistors having the gate dielectric of the first thickness, and a plurality of second transistors having the gate dielectric of the second thickness.
Claim 19
Dependent Claim
15 words
The method of claim 10, wherein step (D) includes depositing a layer of silicon oxide.
References Cited (Backward Citations)
US4471373A
Cited
US4766088A
Cited
US4780424A
Cited
US5104819A
Cited
US5188976A
Cited
US5514889A
Cited
US5340764A
Cited
US5292681A
Cited
US5576226A
Cited
US5591681A
Cited
US5432114A
Cited
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2002-01-04 | 2002-07-06 | 2003-01-05 | $2000.00 | Window Closed / Lapsed |
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