Vector word shift by vo shift count in vector supercomputer processor

Claim 2

In a pipelined vector register computer, a method of moving a contiguous set of operands from a location in a vector register to another location in the vector register, the method comprising the steps of: (a) loading the vector register with a plurality of operands, including a first operand, a second operand, and a third operand; (b) selecting a subset of the plurality of operands by specifying a starting location in the vector register and a number of the operands to be transferred; (c) transferring the first operand to a vector shift functional unit; (d) if the first operand is not within the subset, then discarding the first operand and simultaneously transferring the second operand to the vector shift unit; (e) if the first operand is within the subset, then moving the first operand to a sequential location in the vector register beginning at a fixed first location and simultaneously transferring the second operand to the vector shift unit; and (f) halting the transferring of operands to the vector shift functional unit when the subset of the plurality of operands has been transferred to the vector shift functional unit.

Claim 3

The method according to claim 1, wherein step (d) further comprises the substep of inhibiting a GO WRITE signal, and step (e) further comprises the substep of simultaneously generating the GO WRITE signal.

Claim 4

In a pipelined vector register computer, a method of moving a contiguous set of words from a location in a first vector register to another location in a second vector register, the method comprising the steps of: (a) loading the first vector register with a plurality of words, including a first word, a second word, and a third word; (b) selecting a subset of the plurality of words by specifying a starting location in the first vector register and a number of the words to be transferred; (c) transferring the first word to a vector shift functional unit; (d) if the first word was transferred from a location in the first vector register which lies before the starting location in the first vector register then discarding the first word and simultaneously transferring the second word to the vector shift functional unit; (e) if the first word was transferred from the subset of the plurality of words then moving the first word from the vector shift functional unit to a sequential location in the second vector register beginning at a fixed first location and simultaneously transferring the second word to the vector shift functional unit; and (f) halting the transferring of the plurality of words to the vector shift functional unit when the number of words to be moved has been moved to the second vector register.

Claim 5

In a pipelined vector register computer, a method of moving a contiguous set of words from a location in a first vector register to another location in a second vector register, the method comprising the steps of: (a) loading the first vector register with a plurality of words, including a first word, a second word, and a third word; (b) selecting a subset of the plurality of words by specifying a starting location in the first vector register and a number of the words to be transferred; (c) transferring the first word to a vector shift functional unit; (d) if the first word was transferred from a location in the first vector register which lies before the starting location in the first vector register then discarding the first word and simultaneously transferring the second word to the vector shift functional unit; (e) if the first word was transferred from the subset of the plurality of words then moving the first word from the vector shift functional unit to a sequential location in the second vector register beginning at a fixed first location and simultaneously transferring the second word to the vector shift functional unit; and (f) halting the transferring of the plurality of words to the vector shift functional unit when the number of words to be moved has been moved to the second vector register.

Claim 6

The method according to claim 3, wherein step (d) further comprises the substep of inhibiting a GO WRITE signal, and step (e) further comprises the substep of simultaneously generating the GO WRITE signal.