Computer system for directly transferring vactor elements from register to register using a single instruction

Claim 2

Vector processing apparatus for a computer of the type which performs an operation in accordance with an instruction, said apparatus comprising: instruction receiving means for receiving an instruction from said computer; first storage means for storing a plurality of data elements; second storage means for storing a plurality of data elements; read addressing means responsive to said instruction received by said receiving means for providing read addresses to one of said first and second storage means for reading out data elements therefrom, wherein said read addressing means comprises: a read address register for providing said read addresses to said one storage means; incrementing means coupled to said read address register for incrementing the read address currently in said read address register to obtain an incremented read address; first means for providing a read start address; and read address selector means coupled to said incrementing means and coupled to said first means and responsive to said instruction for first providing said read start address and thereafter providing said incremented read address to said read address register, wherein said instruction includes a field containing said read start address, wherein said first means comprises means for providing a predetermined read start address and means for selectively providing one of said predetermined read start address and said address contained in said field of said instruction; said vector processing apparatus further comprising: write addressing means responsive to said instruction received by said receiving means for providing write addresses to the other of said first and second storage means for writing into said other storage means the data elements read out of said one storage means; and selector means coupled to inputs and outputs of both of said first and second storage means and responsive to said instruction for passing the output from said one storage means to the input of said other storage means.

Claim 3

A vector processing apparatus as claimed in claim 1, wherein said instruction includes a field designating said one of said first and second storage means as a source storage means, and wherein said read addressing means comprises means responsive to said field for selectively providing said read addresses to the storage means designated as said source storage means.

Claim 4

A vector processing apparatus as claimed in claim 2, wherein said read addressing means comprises: a first read address generation circuit for generating said read addresses for said first storage means when activated; a second read address generation circuit for generating said read addresses for said second storage means when activated; and read address control means controlled by said instruction for selectively activating one of said first and second read address generation circuits.

Claim 5

A vector processing apparatus as claimed in claim 1, wherein said selector means receives as first and second inputs the outputs from said first and second storage means, respectively, and receives a third input from a memory in said computer and a fourth input from a processing means in said computer, said selector means having output means coupled to said first and second storage means and being responsive to said instruction for selectively providing any one of its first through fourth inputs to the one of said first and second storage means designated by said instruction as a destination storage means.

Claim 6

A vector processing apparatus as claimed in claim 1, wherein said computer is of the type including a computer main memory, said first and second storage means being separate from said main memory.

Claim 7

A vector processing apparatus as claimed in claim 1, wherein said computer is of the type including at least one functional unit for processing data, and said reading of data elements out of said first storage means and writing of data elements into said second storage means is performed independently of any functional unit in said computer.

Claim 8

Vector processing apparatus for a computer of the type which performs an operation in accordance with an instruction, said apparatus comprising: instruction receiving means for receiving an instruction from said computer; first storage means for storing a plurality of data elements; second storage means for storing a plurality of data elements; read addressing means responsive to said instruction received by said receiving means for providing read addresses to one of said first and second storage means for reading out data elements therefrom; write addressing means responsive to said instruction received by said receiving means for providing write addresses to the other of said first and second storage means for writing into said other storage means the data elements read out of said one storage means, wherein said write addressing means comprises: a write address register for providing said write addresses to said other of said first and second storage means; incrementing means coupled to said write address register for incrementing the write address currently in said write address register to obtain an incremented write address; first means for providing a write start address; and write address selector means coupled to said first means and coupled to said incrementing means and responsive to said instruction for first providing said write start address and thereafter providing said incremented write address to said write address register; said vector processing apparatus further comprising selector means coupled to inputs and outputs of both of said first and second storage means and responsive to said instruction for passing the output from said one storage means to the input of said other storage means, wherein said instruction includes a field containing said write start address and said first means comprises means for providing a predetermined write start address and means for selectively providing one of said predetermined write start address and said address contained in said field of said instruction.

Claim 9

Vector processing apparatus for a computer of the type which performs an operation in accordance with an instruction, said apparatus comprising: instruction receiving means for receiving an instruction from said computer; first storage means for storing a plurality of data elements; second storage means for storing a plurality of data elements; read addressing means responsive to said instruction received by said receiving means for providing read addresses to one of said first and second storage means for reading out data elements therefrom; write addressing means responsive to said instruction received by said receiving means for providing write addresses to the other of said first and second storage means for writing into said other storage means the data elements read out of said one storage means, wherein said write addressing means comprises: a write address register for providing said write addresses to said other of said first and second storage means; incrementing means coupled to said write address register for incrementing the write address currently in said write address register to obtain an incremented write address; first means for providing a write start address; and write address selector means coupled to said first means and coupled to said incrementing means and responsive to said instruction for first providing said write start address and thereafter providing said incremented write address to said write address register; said vector processing apparatus further comprising selector means coupled to inputs and outputs of both of said first and second storage means and responsive to said instruction for passing the output from said one storage means to the input of said other storage means, wherein said instruction includes a field containing said write start address and said first means comprises means for providing a predetermined write start address and means for selectively providing one of said predetermined write start address and said address contained in said field of said instruction.

Claim 10

Vector processing apparatus for a computer of the type which performs an operation in accordance with an instruction, said apparatus comprising: instruction receiving means for receiving an instruction from said computer; first storage means for storing a plurality of data elements; second storage means for storing a plurality of data elements; read addressing means responsive to said instruction received by said receiving means for providing read addresses to one of said first and second storage means for reading out data elements therefrom; write addressing means responsive to said instruction received by said receiving means for providing write addresses to the other of said first and second storage means for writing into said other storage means the data elements read out of said one storage means, wherein said instruction includes a field designating said one of said first and second storage means as a destination storage means, wherein said write addressing means comprises: means responsive to said field for selectively providing said write addresses to the storage means designated as said destination storage means; a first write address generation circuit for generating said write addresses for said first storage means when activated; a second write address generation circuit for generating said write addresses for said second storage means when activated; and write address control means controlled by said instruction for selectively activating one of said first and second write address generation circuits; wherein said vector processing apparatus further comprises selector means coupled to inputs and outputs of both of said first and second storage means and responsive to said instruction for passing the output from said one storage means to the input of said other storage means.

Claim 11

Vector processing apparatus for a computer of the type which performs an operation in accordance with an instruction, said apparatus comprising: instruction receiving means for receiving an instruction from said computer; first storage means for storing a plurality of data elements; second storage means for storing a plurality of data elements; read addressing means responsive to said instruction received by said receiving means for providing read addresses to one of said first and second storage means for reading out data elements therefrom; write addressing means responsive to said instruction received by said receiving means for providing write addresses to the other of said first and second storage means for writing into said other storage means the data elements read out of said one storage means, wherein said instruction includes a field designating said one of said first and second storage means as a destination storage means, wherein said write addressing means comprises: means responsive to said field for selectively providing said write addresses to the storage means designated as said destination storage means; a first write address generation circuit for generating said write addresses for said first storage means when activated; a second write address generation circuit for generating said write addresses for said second storage means when activated; and write address control means controlled by said instruction for selectively activating one of said first and second write address generation circuits; wherein said vector processing apparatus further comprises selector means coupled to inputs and outputs of both of said first and second storage means and responsive to said instruction for passing the output from said one storage means to the input of said other storage means.