US4755931A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Vector processing unit capable of reading vector data from a vector register simultaneously to plural resources
Assignee: Hitachi Ltd
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Filing: 1984-12-21
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Granted: 1988-07-05
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Expires: 2004-12-21
Abstract
Abstract In a vector processing unit, a vector register undergoing the first readout operation is simultaneously subjected to the second reading operation. The data obtained by the first readout operation and the data obtained by the second readout operation are respectively sent to separate resources executing different instructions.
Inventors
- 👤 Hitoshi Abe
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 03:38
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/76; G06F15/80; G06F15/8053; G06F15/8076; G06F9/00; G06F9/06; G06F9/30; G06F9/30003; G06F9/30007; G06F9/30036; G06F9/30038; G06F9/30098; G06F9/30105; G06F9/30109
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
202 words
A vector processing unit, comprising: vector register means including a plurality of vector registers operable independently from each other for storing vector data; a plurality of resources; vector register control means responsive to vector instructions for controlling connections between vector registers designated by said instructions and said resources and for controlling reading/writing of the vector registers to effect data transfer between each vector register and each resource; each vector register comprising a plurality of memory banks operating independently of each other, at least first and second address counter means for generating sequential memory bank addresses to access said memory banks for reading and writing of data, respectively, means for permitting said second addrss counter means to operate for reading of data under control of said vector register control means, and read control means responsive to said vector register control means for sequentially providing addresses alternately from the respective first and second address counter means to respective ones of said plurality of memory banks to read vector data from at least two memory banks simultaneously; and transfer means responsive to said vector instructions for transferring respective data read simultaneously from respective memory banks of the vector register to different ones of said resources.
Claim 2
Dependent Claim
202 words
A vector processing unit, comprising: vector register means including a plurality of vector registers operable independently from each other for storing vector data; a plurality of resources; vector register control means responsive to vector instructions for controlling connections between vector registers designated by said instructions and said resources and for controlling reading/writing of the vector registers to effect data transfer between each vector register and each resource; each vector register comprising a plurality of memory banks operating independently of each other, at least first and second address counter means for generating sequential memory bank addresses to access said memory banks for reading and writing of data, respectively, means for permitting said second addrss counter means to operate for reading of data under control of said vector register control means, and read control means responsive to said vector register control means for sequentially providing addresses alternately from the respective first and second address counter means to respective ones of said plurality of memory banks to read vector data from at least two memory banks simultaneously; and transfer means responsive to said vector instructions for transferring respective data read simultaneously from respective memory banks of the vector register to different ones of said resources.
Claim 3
Dependent Claim
144 words
A vector processing unit according to claim 1, wherein each vector register further comprises an equal number of memory banks and corresponding number of address counter means; wherein said vector register control means includes synchronizing signal generating means responsive to said vector instructions for controlling said read control means of all the vector registers to operate with the same timing so that the respective address counter means among the vector registers address respective memory banks in synchronism; and wherein each vector register further includes delay means responsive to said synchronizing signal generating means for delaying the data output of one of two vector registers designated by one instruction so that data read from the same banks of the two vector registers may be outputted with the same timing when different ones of said respective address counter means in the two vector registers are enabled.
Claim 4
Dependent Claim
125 words
A vector processing unit according to claim 1, wherein said vector register control means includes directive signal generating means responsive to said vector instructions for applying write directive signals to one of said first and second address counter means of a selected vector register in response to a vector instruction designating a vector write operation for said selected vector register and for applying read directive signals to the other one or both of said first and second address counter means of a selected vector register in response to one or more vector instructions designating a read operation for said selected vector register, said first and second address counter means generating sequential memory bank addresses in response to receipt of said read and write directive signals.
Claim 5
Dependent Claim
68 words
A vector processing unit according to claim 3, wherein said directive signal generating means includes administration means for providing status information indicating whether a vector registor is in the process of a single read operation or plural simultaneous read operations, and said vector register control means further includes means responsive to successive vector instructions and said administration means for controlling said administration means to update said status information.
Claim 6
Dependent Claim
144 words
A vector processing unit according to claim 3, wherein each vector register further includes write control means responsive to applicaiton of a write directive signal from said directive signal generating means to said one of said first and second address counter means for generating a write enable signal and for applying said write enable signal in synchronism with the application of said memory bank addresses from said one of said first and second address counter means alternately to said memory banks, so that when write directive signals are supplied to said one of said first and second address counters a write operation is effected on the basis of the generated memory bank addresses, and when read directive signals are supplied to said one of said first and second address counters a read operation is effected on the basis of the generated memory bank addresses.
References Cited (Backward Citations)
US4128880A
Cited
US4302818A
Cited
US4287566A
Cited
US4400768A
Cited
US4435765A
Cited
US4525796A
Cited
US4507728A
Cited
EP0085435A2
Cited
US4636942A
Cited
US4661900A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-07-05 | 1992-01-04 | 1992-07-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-07-05 | 1996-01-04 | 1996-07-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-07-05 | 2000-01-04 | 2000-07-05 | $7700.00 | Window Closed / Lapsed |