Vector processor

Claim 2

A vector processor for executing vector instructions comprising: timing means for providing a timing signal; a plurality of pipeline-type arithmetic logic units, each connected to receive said timing signal, to receive data in a cycle pitch and providing an arithmetic data result in said cycle pitch; a plurality of vector registers each connected to receive said timing signal for executing 2n (n is an integer not less than one) accessing operations in succession during one cycle pitch with respect to a selected vector register; and data transfer means connected between said plurality of pipeline-type arithmetic logic units and said plurality of vector registers for transferring data between said pipeline-type arithmetic logic units and said vector registers.

Claim 3

A vector processor according to claim 1, each of said a plurality of vector registers comprising n write data registers, n read data registers, 2n read/write address registers, and selector means for selecting one of said write data and read data registers and one of said read/write address registers, wherein desired ones of said registers are sequentially selected by use of said selector so that n write operations and n read operations are enabled on the same vector register in one cycle pitch.

Claim 4

A vector processor according to claim 2, wherein each of said vector registers is connected to said selector with two signal lines.

Claim 5

A vector processor for executing vector instructions comprising: timing means for providing a timing signal 2n times during each of a plurality of successive operation cycles (where n is an integer not less than one); a plurality of vector registers, each connected to receive said timing signals and including vector storage means having a plurality of addressable storage locations and read/write control means responsive to said timing signal for executing 2n accessing operations in succession with respect to the storage locations of said vector storage means of a selected vector register during each operation cycle; a plurality of pipeline-type arithmetic logic units, each connected to receive said timing signals and data from selected ones of said plurality of vector registers in an operating cycle for providing an arithmetic data result in one operating cycle; and data transfer means connected between said plurality of pipeline-type arithmetic logic units and said plurality of vector registers for transferring data between said pipeline-type arithmetic logic units and said vector registers under control of said timing signal.

Claim 6

A vector processor for executing vector instructions comprising: timing means for providing a timing signal 2n times during each of a plurality of successive operation cycles (where n is an integer not less than one); a plurality of vector registers, each connected to receive said timing signals and including vector storage means having a plurality of addressable storage locations and read/write control means responsive to said timing signal for executing 2n accessing operations in succession with respect to the storage locations of said vector storage means of a selected vector register during each operation cycle; a plurality of pipeline-type arithmetic logic units, each connected to receive said timing signals and data from selected ones of said plurality of vector registers in an operating cycle for providing an arithmetic data result in one operating cycle; and data transfer means connected between said plurality of pipeline-type arithmetic logic units and said plurality of vector registers for transferring data between said pipeline-type arithmetic logic units and said vector registers under control of said timing signal.

Claim 7

A vector processor according to claim 4, wherein said read/write control means in each of said plurality of vector registers includes n write data registers, n read data registers, n read address registers, n write address registers, and selector means responsive to said timing signal for selectively connecting said write data registers, said read address registers and said write address registers to said vector storage means to sequentially access said addressable storage location so that n write operations and n read operations are performed during one operating cycle.

Claim 8

A vector processor according to claim 5, wherein said selector means includes a first selector connecting said write data registers to said vector storage means, a second selector connecting said read address registers and said write address registers to said vector storage means, and an n bit counter responsive to said timing signal for controlling said first and second selectors.

Claim 9

A vector processor according to claim 4, wherein n=2, and each of said vector registers is connected to said data transfer means by way of two signal lines.

Claim 10

A vector processor according to claim 4, wherein said data transfer means includes a first selector connecting said outputs of said vector registers to inputs of said arithmetic logic units, and a second selector connecting outputs of said arithmetic logic units to inputs of said vector registers.

Claim 11

A vector processor according to claim 4, wherein said read/write control means in each of said plurality of vector register includes n write data registers, n read data registers, n read address registers, n write address registers, (where n is an integer not less than 2) and selector means responsive to said timing signals for selectively connecting said write data registers, said read address registers and said write address registers to said vector storage means to sequentially access a plurality of addressable storage locations of a selected vector storage means so that both a data write operation and a data read operation is effected with respect to each of said sequentially accessed addressable storage locations in one operating cycle.

Claim 12

A vector processor for executing vector instructions comprising: timing means for providing a timing signal a plurality of times during each of a plurality of successive operation cycles; a plurality of vector registers, each connected to receive said timing signals and each including vector storage means having a plurality of addressable storage locations and read/write control means responsive to said timing signals for executing a data write operation and a data read operation in succession with respect to the same storage location of a selected one of said vector storage means during each operation cycle; a plurality of pipeline-type arithmetic logic units, each connected to receive said timing signals and data from selected ones of said plurality of vector registers in an operating cycle for providing an arithmetic data result in one operating cycle; and data transfer means connected between said plurality of pipeline-type arithmetic logic units and said plurality of vector registers for transferring data between said pipeline-type arithmetic logic units and said vector registers under control of said timing signal.

Claim 13

A vector processor for executing vector instructions comprising: timing means for providing a timing signal a plurality of times during each of a plurality of successive operation cycles; a plurality of vector registers, each connected to receive said timing signals and each including vector storage means having a plurality of addressable storage locations and read/write control means responsive to said timing signals for executing a data write operation and a data read operation in succession with respect to the same storage location of a selected one of said vector storage means during each operation cycle; a plurality of pipeline-type arithmetic logic units, each connected to receive said timing signals and data from selected ones of said plurality of vector registers in an operating cycle for providing an arithmetic data result in one operating cycle; and data transfer means connected between said plurality of pipeline-type arithmetic logic units and said plurality of vector registers for transferring data between said pipeline-type arithmetic logic units and said vector registers under control of said timing signal.