US4127899A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Self-quenching memory cell
Assignee: International Business Machines Corp
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Filing: 1977-12-05
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Granted: 1978-11-28
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Expires: 1997-12-05
Abstract
Abstract A memory array comprising a matrix of cells each of which includes a pair of bipolar transistor inverters. The collector loads of the inverters are commonly connected to a first constant voltage buss. The emitters of the transistors are commonly connected through a second resistor to a second constant voltage buss. Separate writing and reading circuits are provided for each cell in the array so that array cells can be written into and read from simultaneously.
Inventors
- 👤 William R. Dachtera
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 20:13
CPC Classifications
G; G11; G11C; G11C8/00; G11C8/16; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/411; G11C11/4113; G11C11/413; G11C11/414
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
149 words
A self-quenching memory cell comprising: a pair of cross-connected transistor inverters, the base of each transistor being connected to the junction of the collector and the collector load of the other transistor, a resistor, first and second constant value voltage sources, said collectors of said transistors being connected by respective ones of said loads to said first voltage source, the emitters of said transistors being connected by said resistor to said second voltage source, the resistance of said resistor being set relative to the effective impedance of said cross-connected transistor inverters so that said resistor and said second voltage source do not provide a constant current to said emitters when data is written into said cell, first actuable means connected to said bases of said transistors for writing data into said cell, and second actuable means connected to said bases of said transistors for reading data from said cell.
Claim 2
Dependent Claim
149 words
A self-quenching memory cell comprising: a pair of cross-connected transistor inverters, the base of each transistor being connected to the junction of the collector and the collector load of the other transistor, a resistor, first and second constant value voltage sources, said collectors of said transistors being connected by respective ones of said loads to said first voltage source, the emitters of said transistors being connected by said resistor to said second voltage source, the resistance of said resistor being set relative to the effective impedance of said cross-connected transistor inverters so that said resistor and said second voltage source do not provide a constant current to said emitters when data is written into said cell, first actuable means connected to said bases of said transistors for writing data into said cell, and second actuable means connected to said bases of said transistors for reading data from said cell.
Claim 3
Dependent Claim
22 words
The memory cell defined in claim 1 wherein each said collector load comprises a resistor connected in parallel with a Schottky diode.
Claim 4
Dependent Claim
119 words
The memory cell defined in claim 1 wherein said second actuable means comprises third, fourth and fifth transistors, the bases of said third and fourth transistors being connected to the bases of said first and second transistors, respectively, the emitters of said third and fourth transistors being connected to the collector of said fifth transistor, said cell further including a pair of read column sense lines a read column driver line and a read word selection line, the collectors of said third and fourth transistors being connected respectively to said sense lines, the emitter of said fifth transistor being connected to said driver line, and the base of said fifth transistor being connected to said read word selection line.
Claim 5
Dependent Claim
86 words
The memory cell defined in claim 1 wherein said first actuable means comprises sixth and seventh transistors, the collectors of said sixth and seventh transistors being connected to the bases of said first and second transistors, respectively, said cell further including, a pair of write column driver lines, and a write word selection line, the emitters of said sixth and seventh transistors being connected respectively to said driver lines, and the bases of said sixth and seventh transistors being connected to said write word selection line.
Claim 6
Dependent Claim
44 words
The memory cell defined in claim 1 wherein each said collector load comprises a resistor connected in parallel with a Schottky diode, and wherein said first actuable means comprises separately actuable means for writing data into said cell from more than one data source.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-11-27 | 1982-05-29 | 1982-11-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-11-27 | 1986-05-29 | 1986-11-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-11-27 | 1990-05-29 | 1990-11-28 | $7700.00 | Window Closed / Lapsed |