US3973246A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Sense-write circuit for bipolar integrated circuit ram
Assignee: Motorola Solutions Inc
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Filing: 1975-07-11
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Granted: 1976-08-03
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Expires: 1995-07-11
Abstract
Abstract A bipolar sense-write circuit is provided for sensing voltage levels representative of a logical "1" or "0" stored in a flip-flop storage cell and for writing voltage levels into the flip-flop storage cell. The sense-write circuit includes first and second amplifier stages which, when coupled to a selected flip-flop storage cell produce a voltage in the amplifier section approximately equal to the voltage on a collector node in the flip-flop storage cell. Each amplifier stage of the sense-write circuit utilizes a side of the selected flip-flop storage cell as a part of that amplifier stage, if the corresponding side of the flip-flop storage cell is "on". The amplifier stage connected to the "on" side of the selected flip-flop storage cell acts as a unity gain amplifier, such that the row selection voltage appears at the output of that amplifier stage. This arrangement allows the data stage of memory cell flip-flop to be sensed without the use of any fixed reference voltage generated external to the memory cell. The arrangement provides the additional benefit of reducing the required difference between the internal memory cell flip-flop voltages, proportionately decreasing the time required to write a given state into the flip-flop memory cell.
Inventors
- 👤 Michael S. Millhollan
- 👤 Ronald L. Treadway
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 09:46
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/01; H03K5/02; G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/411; G11C11/4113; G11C11/4116; G11C11/413; G11C11/414; G11C11/416; H03K3/00; H03K3/02; H03K3/26; H03K3/28; H03K3/281; H03K3/286; H03K3/288
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
446 words
A sense-write circuit for detecting and amplifying a stored logic level and for writing a logic level into a storage circuit, said sense-write circuit being coupled to said logic circuit comprising: a first amplifier circuit including first resistive means and first and second electron control means each having first and second main electrodes and a control electrode; a second amplifier including second resistive means and third and fourth electron control means each having first and second main electrodes and a control electrode; said first resistive means being coupled between a first voltage conductor and an output node of said first amplifier circuit, and first electron control means having a first main electrode coupled to said output node of said first amplifier circuit and said second main electrode connected to a sense-write conductor, said second electron control means being coupled between said first voltage conductor and said control electrode of said first electron control means and having its control electrode coupled to said output node of said first amplifier circuit; said third electron control means and said second resistive means being coupled in series between said first voltage conductor and said second voltage conductor, said control electrode of said third electron control means being coupled to said output node of said first amplifier circuit; said third resistive means being coupled between said first voltage conductor and an output node of said second amplifier circuit, said fourth electron control means being coupled between said output node of said second amplifier circuit and a second sense-write conductor, said fifth electron control means being coupled between said first voltage conductor and said control electrode of said fourth electron control means and having its control electrode coupled to said output node of said second amplifier circuit; said sixth electron control means and said fourth resistive means being coupled in series between said first and second voltage conductors, said control electrode of said sixth electron control means being coupled to said output node of said second amplifier circuit; an input circuit having an input node for receiving a write input signal, said write input circuit being coupled to said control electrode of said first electron control means and to said control electrode of said fourth electron control means; said control electrode of said electron control means being coupled to said control electrode of said fourth electron control means; said second main electrode of said sixth electron control means being coupled to said control electrode of said first electron controls means; said first and second sense-write conductors being coupled to at least one storage circuit, said storage circuit including first and second cross-coupled electron control means and first and second resistive load means.
Claim 2
Dependent Claim
446 words
A sense-write circuit for detecting and amplifying a stored logic level and for writing a logic level into a storage circuit, said sense-write circuit being coupled to said logic circuit comprising: a first amplifier circuit including first resistive means and first and second electron control means each having first and second main electrodes and a control electrode; a second amplifier including second resistive means and third and fourth electron control means each having first and second main electrodes and a control electrode; said first resistive means being coupled between a first voltage conductor and an output node of said first amplifier circuit, and first electron control means having a first main electrode coupled to said output node of said first amplifier circuit and said second main electrode connected to a sense-write conductor, said second electron control means being coupled between said first voltage conductor and said control electrode of said first electron control means and having its control electrode coupled to said output node of said first amplifier circuit; said third electron control means and said second resistive means being coupled in series between said first voltage conductor and said second voltage conductor, said control electrode of said third electron control means being coupled to said output node of said first amplifier circuit; said third resistive means being coupled between said first voltage conductor and an output node of said second amplifier circuit, said fourth electron control means being coupled between said output node of said second amplifier circuit and a second sense-write conductor, said fifth electron control means being coupled between said first voltage conductor and said control electrode of said fourth electron control means and having its control electrode coupled to said output node of said second amplifier circuit; said sixth electron control means and said fourth resistive means being coupled in series between said first and second voltage conductors, said control electrode of said sixth electron control means being coupled to said output node of said second amplifier circuit; an input circuit having an input node for receiving a write input signal, said write input circuit being coupled to said control electrode of said first electron control means and to said control electrode of said fourth electron control means; said control electrode of said electron control means being coupled to said control electrode of said fourth electron control means; said second main electrode of said sixth electron control means being coupled to said control electrode of said first electron controls means; said first and second sense-write conductors being coupled to at least one storage circuit, said storage circuit including first and second cross-coupled electron control means and first and second resistive load means.
Claim 3
Dependent Claim
84 words
The sense-write circuit as recited in claim 1 wherein said write circuit includes seventh and eighth electron control means, said seventh electron control means being coupled between said first voltage conductor and said control electrode of said first electron control means and its control electrode coupled to a said write conductor, said eighth electron control means having a control electrode coupled to a second write conductor and being coupled between said first voltage conductor and said control electrode of said fourth electron control means.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-08-03 | 1980-02-02 | 1980-08-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-08-03 | 1984-02-02 | 1984-08-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-08-03 | 1988-02-02 | 1988-08-03 | $7700.00 | Window Closed / Lapsed |