Memory cell for an associative memory

Claim 2

A memory element comprising: control means for providing first, second, and third voltage levels; a bistable circuit comprising a pair of cross coupled switch elements, each switch element respectively coupled to said control means; means for interrogating said bistable circuit comprising a current generating source and a current sensing device; two output buffer means each having a first terminal connected to one of said cross coupled switch elements, a second terminal connected to said interrogate means, and a third terminal, whereby said control means provides the first voltage level signal to said bistable circuit to maintain said bistable circuit in a stable conducting state, and said control means provides the second voltage level signal to said bistable circuit so as to cause conduction between the second and third terminals of one of said two output buffer means to thus indicate the particular binary stored contents within said bistable circuit; logic means, connected to the third terminals of each of said two output buffer means, for selectively modifying the voltage level at the third terminal of each output buffer means, whereby said logic means selectively modifies the voltage at a selected third terminal of one of said output buffer means and said control means provides the third voltage level signal to said bistable circuit so as to cause conduction between the second and third terminals of the non-selected output buffer means to thereby draw current from said interrogate means down through the first and third terminals of the then conducting non-selected output buffer means only when the selective modification by said lOgic means differs from the actual stored content of said bistable circuit.

Claim 3

The memory element of claim 1 wherein said logic means comprises: means for back biasing said output buffer means; means for selectively modifying the back bias on said output buffer means said back bias modifying means connected to said output buffer means and to said back biasing means, said back bias modifying means operative to modify the back biasing on the third terminal of either of said output buffer means.

Claim 4

The memory element of claim 2 wherein each of said output buffer means comprises a transistor wherein the first terminal is the base of the transistor, the second terminal is the collector of the transistor, and the third terminal is the emitter of the transistor.

Claim 5

The memory element of claim 3 further comprising: means for sensing the conductive state of either of said two output buffer means so as to sense the particular stored value within said bistable circuit, said sensing means connected to the third terminals of each of said output buffer means.

Claim 6

A memory cell capable of functioning in the read, write, standby and interrogate modes of operation comprising: control means for providing a first voltage level for the standby mode of operation, a second voltage level for the read and write modes of operation, and a third voltage level for the interrogate mode of operation; a bistable circuit respectively coupled to said control means comprising a pair of cross coupled first and second transistors each of which is emitter coupled to a negative voltage source; output buffer means connected to said bistable circuit, said output buffer means operative to output a binary current indication of the presently stored contents of said bistable circuit in response to said control means providing a second voltage level signal to said bistable circuit; current sensing means coupled to said output buffer means for sensing the binary current indication of the presently stored contents of said bistable circuit means coupled to said output buffer means for normally back biasing said output buffer means; means for selectively modifying the normal back bias on said output buffer means, said selective modifying means connected to said output buffer means and to said back biasing means, said selective modifying means operative to modify the normal back biasing on said output buffer means by grounding one side of said output buffer means in response to a particular write binary number operation command, and operative to ground the opposite side of said output buffer means in response to an interrogate operation command for the same binary member; and interrogate sensing means, connected to said output buffer means, said interrogate sensing means comprising a voltage source and a current sensing means, said current sensing means interposed between said voltage source and said output buffer means and operative to sense any current drawn by said output buffer means during an interrogation operation when said selective modifying means selects a particular side of said output buffer means.

Claim 7

A memory cell capable of functioning in the read, write, standby and interrogate modes of operation comprising: control means for providing a first voltage level for the standby mode of operation, a second voltage level for the read and write modes of operation, and a third voltage level for the interrogate mode of operation; a bistable circuit respectively coupled to said control means comprising a pair of cross coupled first and second transistors each of which is emitter coupled to a negative voltage source; output buffer means connected to said bistable circuit, said output buffer means operative to output a binary current indication of the presently stored contents of said bistable circuit in response to said control means providing a second voltage level signal to said bistable circuit; current sensing means coupled to said output buffer means for sensing the binary current indication of the presently stored contents of said bistable circuit means coupled to said output buffer means for normally back biasing said output buffer means; means for selectively modifying the normal back bias on said output buffer means, said selective modifying means connected to said output buffer means and to said back biasing means, said selective modifying means operative to modify the normal back biasing on said output buffer means by grounding one side of said output buffer means in response to a particular write binary number operation command, and operative to ground the opposite side of said output buffer means in response to an interrogate operation command for the same binary member; and interrogate sensing means, connected to said output buffer means, said interrogate sensing means comprising a voltage source and a current sensing means, said current sensing means interposed between said voltage source and said output buffer means and operative to sense any current drawn by said output buffer means during an interrogation operation when said selective modifying means selects a particular side of said output buffer means.

Claim 8

The memory cell of claim 5 wherein said output buffer means comprises: a pair of output buffer transistors, each output buffer transistor being base connected to one of said pair of cross coupled first and second transistors, and furthermore being collector connected to said interrogate means and emitter connected to said back biasing means.

Claim 9

The memory cell of claim 6 wherein said means for selectively modifying the normal back bias on said output buffer means comprises: a pair of normally non-conducting transistors each of which is collector connected to a respective output buffer means and emitter connected to ground; and means for turning either normally non-conducting transistor on to thereby cause the corresponding collector connected output buffer means to be grounded.

Claim 10

A memory cell capable of functioning in the Read, write, standby and interrogate modes of operation comprising: control means for providing a first voltage level for the standby mode of operation, a second voltage level for the read and write modes of operation, and a third voltage level for the interrogate mode of operation; a bistable circuit comprising a pair of cross coupled first and second transistors each of which is emitter coupled to a negative voltage source; a control line connecting said control means to said bistable circuit; an interrogate sense means connected to said control line for sensing any current change in the control line during the interrogate mode of operation; output buffer means connected to said bistable circuit, said output buffer means operative to output a binary current indication of the presently stored contents of said bistable circuit in response to said control means providing a second voltage level to said bistable circuit; current sensing means coupled to said output buffer means for sensing the binary current indication of the presently stored contents of said bistable circuit; means coupled to said output buffer means for normally back biasing said output buffer means; and means for selectively modifying the normal back bias of said output buffer means, said selective modifying means operative to modify the back biasing on said output buffer means so as to alter the current flow normally present in said control line depending on whether a mismatch occurs during an interrogate operation.

Claim 11

A memory cell capable of functioning in the Read, write, standby and interrogate modes of operation comprising: control means for providing a first voltage level for the standby mode of operation, a second voltage level for the read and write modes of operation, and a third voltage level for the interrogate mode of operation; a bistable circuit comprising a pair of cross coupled first and second transistors each of which is emitter coupled to a negative voltage source; a control line connecting said control means to said bistable circuit; an interrogate sense means connected to said control line for sensing any current change in the control line during the interrogate mode of operation; output buffer means connected to said bistable circuit, said output buffer means operative to output a binary current indication of the presently stored contents of said bistable circuit in response to said control means providing a second voltage level to said bistable circuit; current sensing means coupled to said output buffer means for sensing the binary current indication of the presently stored contents of said bistable circuit; means coupled to said output buffer means for normally back biasing said output buffer means; and means for selectively modifying the normal back bias of said output buffer means, said selective modifying means operative to modify the back biasing on said output buffer means so as to alter the current flow normally present in said control line depending on whether a mismatch occurs during an interrogate operation.

Claim 12

The memory cell of claim 8 wherein said interrogate sense means comprises: means for sampling and holding the current present in said control line immediately prior to initiating an interrogation of the contents of the memory cell; means for measuring the current present in said control line during the interrogation of the contents of the memory cell; and means connected to said sample and hold means and to said measuring means for detecting any difference between the current measurement made during the interrogation as outputed by said measuring means and the current present in the control line prior to initiating the interrogation operation as outputed by said sample and hold means.

Claim 13

The memory cell of claim 9 further comprising: means, connected to said control means and to said selective modifying means, for activating said selective modifying means after a time delay of time T which is equal to or greater than the time required to sample and hold the current normally present in the control line prior to any interrogation of the memory cell.

Claim 14

The associative memory array of claim 11 wherein each of said interrogate sense means comprises a voltage source and a current sensing means, said current sensing means interposed between said voltage source and the output buffer means within the particular word group of bistable circuits.

Claim 15

The associative memory array of claim 12 wherein each of said bistable circuits comprises: a pair of cross coupled first and second transistors each of which is emitter coupled to a negative voltage source.

Claim 16

The associative memory array of claim 13 wherein each of said output buffer means comprises: a pair of output buffer transistors, each output buffer transistor being base connected to one of said pair of cross coupled first and second transistors, and furthermore being collector connected to said interrogate means and emitter connected to said back biasing means.

Claim 17

The associative memory array of claim 14 wherein each of said means for selectively modifying the normal back bias on said output buffer means comprises: a pair of normally non-conducting transistors each of which is collector connected to a respective output buffer means and emitter connected to ground; and means for turning either normally non-conducting transistor on to thereby cause the corresponding collector connected output buffer means to be grounded.