EP0167959A2
Expired / Lapsed
EP
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Computer vector register processing
Assignee: NEC Corp
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Filing: 1985-07-01
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Granted: —
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Expires: 2005-07-01
Abstract
Abstract The movement of a set of element data in a computer is achieved by means of a plurality of vector registers (100, 101) and a moving unit which can move a set of element data from one vector register (100) to another register (101) in response to one instruction without going through either main memory or the functional units. A selector (200) responds to the instruction to route the output from one register (100) to the input of another and to also provide the appropriate read and write starting addresses.
Inventors
- 👤 Hiroyuki Izumisawa
- 👤 Seiichiro Kinoshita
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-08 15:24
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/30003; G06F9/30007; G06F9/30032; G06F15/00; G06F15/76; G06F15/80; G06F15/8053; G06F15/8076; G06F9/30036; G06F9/30098
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
124 words
Vector processing apparatus for a computer, said apparatus comprising: first storage means for storing a plurality of data elements; second storage means for storing a plurality of data elements; read addressing means for providing read addresses to one of said first and second storage means for reading out data elements therefrom; write addressing means for providing write addresses to the other of said first and second storage means for writing into said other storage means the data elements read out of said one storage means; and selector means coupled to inputs and outputs of both of said first and second storage means and responsive to an instruction for passing the output from said one storage means to the input of said other storage means.
Claim 2
Dependent Claim
124 words
Vector processing apparatus for a computer, said apparatus comprising: first storage means for storing a plurality of data elements; second storage means for storing a plurality of data elements; read addressing means for providing read addresses to one of said first and second storage means for reading out data elements therefrom; write addressing means for providing write addresses to the other of said first and second storage means for writing into said other storage means the data elements read out of said one storage means; and selector means coupled to inputs and outputs of both of said first and second storage means and responsive to an instruction for passing the output from said one storage means to the input of said other storage means.
Claim 3
Dependent Claim
83 words
A vector processing apparatus as claimed in claim 1, wherein said read addressing means comprises a read address register for providing said read addresses to said one storage means; incrementing means for incrementing the read address currently in said read address register to obtain an incremented read address; means for providing a read start address; and read address selector means responsive to said instruction for first providing said read start address and thereafter providing said incremented read address to said read address register.
Claim 4
Dependent Claim
54 words
A vector processing apparatus as claimed in claim 1 or 2, wherein said instruction includes a field for designating said read start address and said means for providing said read start address comprises means for selectively providing one of a predetermined read start address and said address specified by said field of said instruction.
Claim 5
Dependent Claim
62 words
A vector processing apparatus as claimed in any of claims 1 to 3, wherein said instruction includes a field designating said one of said first and second storage means as a source storage means, and wherein said read addressing means comprises means responsive to said field for selectively providing said read addresses to the storage means designated as said source storage means.
Claim 6
Dependent Claim
62 words
A vector processing apparatus as claimed in any of claims 1 to 4, wherein said read addressing means comprises a first read address generation circuit for said first storage means and a second read address generation circuit for said second storage means, said selector means selectively activating one of said first and second read address generation circuits in accordance with said instruction.
Claim 7
Dependent Claim
87 words
A vector processing apparatus as claimed in any of claims 1 to 5, wherein said write addressing means comprises a write address register for providing said write addresses to said one storage means; incrementing means for incrementing the write address currently in said write address register to obtain an incremented write address; means for providing a write start address; and write address selector means responsive to said instruction for first providing said write start address and thereafter providing said incremented write address to said write address register.
Claim 8
Dependent Claim
56 words
A vector processing apparatus as claimed in any of claims 1 to 6, wherein said instruction includes a field for designating said write start address and said means for providing said write start address comprises means for selectively providing one of a predetermined write start address and said address specified by said field of said instruction.
Claim 9
Dependent Claim
62 words
A vector processing apparatus as claimed in any of claims 1 to 7, wherein said instruction includes a field designating said one of said first and second storage means as a destination storage means, and wherein said write addressing means comprises means responsive to said field for selectively providing said write addresses to the storage means designated as said destination storage means.
Claim 10
Dependent Claim
62 words
A vector processing apparatus as claimed in any of claims 1 to 8, wherein said write addressing means comprises a first write address generation circuit for said first storage means and a second write address generation circuit for said second storage means, said selector means selectively activating one of said first and second write address generation circuits in accordance with said instruction.
Claim 11
Dependent Claim
93 words
A vector processing apparatus as claimed in any of claims 1 to 9, wherein said selector means receives as first and second inputs the outputs from said first and second storage means, respectively, and receives a third input from a memory in said computer and a fourth input from a processing means in said computer, said selector means being responsive to said instruction for selectively providing any one of its first through fourth inputs to the one of said first and second storage means designated by said instruction as a destination storage means.
Claim 12
Dependent Claim
75 words
Vector processing apparatus for a computer, said apparatus comprising: first storage means for storing a plurality of data elements ; second storage means for storing a plurality of data elements ; and means responsive to a single instruction for selectively designating one of said first and second storage means as a destination storage means and for selectively moving a plurality of data elements from said one storage means to the other of said storage means.
Claim 13
Dependent Claim
75 words
Vector processing apparatus for a computer, said apparatus comprising: first storage means for storing a plurality of data elements ; second storage means for storing a plurality of data elements ; and means responsive to a single instruction for selectively designating one of said first and second storage means as a destination storage means and for selectively moving a plurality of data elements from said one storage means to the other of said storage means.
References Cited (Backward Citations)
No citation records indexed.
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