Patent US5847578A successfully refreshed from Google Patents.
US5847578A
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US
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Programmable multiplexing input/output port
Assignee: Mentor Graphics Corp
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Filing: 1997-01-08
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Granted: 1998-12-08
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Expires: 2017-01-08
Abstract
Abstract A programmable logic circuit includes a programmable logic array which generates a plurality of output signals for output from a single port on the programmable logic circuit, and which processes a plurality of input signals received from a single port on the programmable logic circuit. The programmable logic circuit also includes multiplexing means for receiving the plurality of output signals generated by the programmable logic array and for multiplexing the plurality of output signals. An output port outputs, from the programmable logic circuit, the multiplexed plurality of output signals generated by the programmable logic array. An input port receives a multiplexed plurality of input signals, and a demultiplexing means demultiplexes the multiplexed plurality of input signals and configurably communicates the demultiplexed plurality of input signals to the programmable logic array. This demultiplexing means and the multiplexing means are each operable at a clock speed which is different from a clock speed of the programmable logic array.
Inventors
- 👤 Michael Donald Noakes
- 👤 Charles W. Selvidge
- 👤 Anant Argarwal
- 👤 Jonathan Babb
- 👤 Matthew L. Dahl
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 07:49
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/34; H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/1731; H03K19/1732; H03K19/1733; H03K19/1737
Claims Analysis
Total Claims: 33
Claim 1
Independent Claim
168 words
A programmable logic circuit having a programmable logic array which generates a plurality of output signals for output from a single port on the programmable logic circuit, and which processes a plurality of input signals received from a single port on the programmable logic circuit, the programmable logic circuit comprising: multiplexing means for receiving the plurality of output signals generated by the programmable logic array and for multiplexing said plurality of output signals; an output port for outputting from the programmable logic circuit, the multiplexed plurality of output signals generated by the programmable logic array; an input port for receiving a multiplexed plurality of input signals; and demultiplexing means for demultiplexing said multiplexed plurality of input signals, and for configurably communicating said demultiplexed plurality of input signals to the programmable logic array; wherein the programmable logic array is operable at a first clock speed and wherein the multiplexing means and the demultiplexing means are each operable at a clock speed which is different from the first clock speed.
Claim 2
Dependent Claim
168 words
A programmable logic circuit having a programmable logic array which generates a plurality of output signals for output from a single port on the programmable logic circuit, and which processes a plurality of input signals received from a single port on the programmable logic circuit, the programmable logic circuit comprising: multiplexing means for receiving the plurality of output signals generated by the programmable logic array and for multiplexing said plurality of output signals; an output port for outputting from the programmable logic circuit, the multiplexed plurality of output signals generated by the programmable logic array; an input port for receiving a multiplexed plurality of input signals; and demultiplexing means for demultiplexing said multiplexed plurality of input signals, and for configurably communicating said demultiplexed plurality of input signals to the programmable logic array; wherein the programmable logic array is operable at a first clock speed and wherein the multiplexing means and the demultiplexing means are each operable at a clock speed which is different from the first clock speed.
Claim 3
Dependent Claim
27 words
A programmable logic circuit according to claim 1, further comprising a pin electrically coupled to said output port and a pin electrically coupled to said input port.
Claim 4
Dependent Claim
27 words
A programmable logic circuit according to claim 2, further comprising means for outputting a select signal to select one of said output port or said input port.
Claim 5
Dependent Claim
32 words
A programmable logic circuit according to claim 1, further comprising multiplexing control means for controlling said multiplexing means to operate at a clock speed which is greater than the first clock speed.
Claim 6
Dependent Claim
32 words
A programmable logic circuit according to claim 1, further comprising demultiplexing control means for controlling said demultiplexing means to operate at a clock speed which is greater than the first clock speed.
Claim 7
Dependent Claim
57 words
A programmable logic circuit according to claim 2 or 3, further comprising: multiplexing control means for controlling said multiplexing means to operate at a clock speed which is greater than the first clock speed; and demultiplexing control means for controlling said demultiplexing means to operate at a clock speed which is greater than the first clock speed.
Claim 8
Dependent Claim
27 words
A programmable logic circuit according to claim 4 or 5, wherein said multiplexing control means and said demultiplexing control means are external to said programmable logic array.
Claim 9
Dependent Claim
25 words
A programmable logic circuit according to claim 6, wherein said multiplexing control means and said demultiplexing control means are external to said programmable logic array.
Claim 10
Dependent Claim
17 words
A programmable logic circuit according to claim 1, wherein said multiplexing means comprises at least one flip-flop.
Claim 11
Dependent Claim
17 words
A programmable logic circuit according to claim 1, wherein said multiplexing means comprises at least one latch.
Claim 12
Dependent Claim
16 words
A programmable logic circuit according to claim 3, wherein said demultiplexing means comprises a shift register.
Claim 13
Dependent Claim
22 words
A programmable logic circuit according to claim 1 or 2, wherein the programmable logic array in said programmable logic circuit is reconfigurable.
Claim 14
Dependent Claim
20 words
A programmable logic circuit according to claim 6, wherein the programmable logic array in said programmable logic circuit is reconfigurable.
Claim 15
Dependent Claim
18 words
A programmable logic circuit according to claim 4 or 5, wherein said programmable logic circuit is an FPGA.
Claim 16
Dependent Claim
16 words
A programmable logic circuit according to claim 6, wherein said programmable logic circuit is an FPGA.
Claim 17
Dependent Claim
24 words
A programmable logic circuit according to claim 15, wherein said multiplexing control means and said demultiplexing control means are each comprised of programmable logic.
Claim 18
Independent Claim
134 words
A method of inputting and outputting a plurality of signals from a programmable logic circuit which includes a programmable logic array that generates a plurality of output signals and that processes a plurality of input signals, the method comprising the steps of: multiplexing the plurality of output signals generated by the programmable logic array; outputting the multiplexed plurality of output signals from the programmable logic circuit; receiving a multiplexed plurality of input signals at the programmable logic circuit; demultiplexing the multiplexed plurality of input signals; and communicating the demultiplexed plurality of input signals to the programmable logic array; wherein the programmable logic array is operable at a first clock speed and wherein the multiplexing steps and the demultiplexing steps are each performed at a clock speed which is different from the first clock speed.
Claim 19
Independent Claim
134 words
A method of inputting and outputting a plurality of signals from a programmable logic circuit which includes a programmable logic array that generates a plurality of output signals and that processes a plurality of input signals, the method comprising the steps of: multiplexing the plurality of output signals generated by the programmable logic array; outputting the multiplexed plurality of output signals from the programmable logic circuit; receiving a multiplexed plurality of input signals at the programmable logic circuit; demultiplexing the multiplexed plurality of input signals; and communicating the demultiplexed plurality of input signals to the programmable logic array; wherein the programmable logic array is operable at a first clock speed and wherein the multiplexing steps and the demultiplexing steps are each performed at a clock speed which is different from the first clock speed.
Claim 20
Dependent Claim
37 words
A method according to claim 17, wherein the programmable logic circuit includes a single input port for receiving the multiplexed plurality of input signals and a single output port for outputting the multiplexed plurality of output signals.
Claim 21
Dependent Claim
26 words
A method according to claim 18, further comprising the step of outputting a select signal to select one of the output port or the input port.
Claim 22
Dependent Claim
29 words
A method according to claim 17, further comprising the step of controlling the multiplexing step to operate at a clock speed which is greater than the first clock speed.
Claim 23
Dependent Claim
29 words
A method according to claim 17, further comprising the step of controlling the demultiplexing step to operate at a clock speed which is greater than the first clock speed.
Claim 24
Dependent Claim
50 words
A method according to claim 18 or 19, further comprising the steps of: controlling the multiplexing step to operate at a clock speed which is greater than the first clock speed; and controlling the demultiplexing step to operate at a clock speed which is greater than the first clock speed.
Claim 25
Dependent Claim
58 words
A method according to claim 20 or 21, wherein the multiplexing step is performed by a multiplexing means which is controlled by a control means that is external to the programmable logic array, and the demultiplexing step is performed by a demultiplexing means which is controlled by a control means that is external to the programmable logic array.
Claim 26
Dependent Claim
56 words
A method according to claim 22, wherein the multiplexing step is performed by a multiplexing means which is controlled by a control means that is external to the programmable logic array, and the demultiplexing step is performed by a demultiplexing means which is controlled by a control means that is external to the programmable logic array.
Claim 27
Dependent Claim
15 words
A method according to claim 24, wherein the multiplexing means comprises at least one flip-flop.
Claim 28
Dependent Claim
15 words
A method according to claim 24, wherein the multiplexing means comprises at least one latch.
Claim 29
Dependent Claim
14 words
A method according to claim 24, wherein the demultiplexing means comprises a shift register.
Claim 30
Dependent Claim
36 words
A method according to claim 17 or 18, further comprising the step of reconfiguring the programmable logic array in the programmable logic circuit to affect generation of the output signals or processing of the input signals.
Claim 31
Dependent Claim
34 words
A method according to claim 22, further comprising the step of reconfiguring the programmable logic array in the programmable logic circuit to affect generation of the output signals or processing of the input signals.
Claim 32
Dependent Claim
16 words
A method according to claim 20 or 21, wherein the programmable logic circuit is an FPGA.
Claim 33
Dependent Claim
14 words
A method according to claim 22, wherein the programmable logic circuit is an FPGA.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-12-07 | 2002-06-08 | 2002-12-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-12-07 | 2006-06-08 | 2006-12-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-12-07 | 2010-06-08 | 2010-12-08 | $7700.00 | Window Closed / Lapsed |