US5111455A
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US
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Interleaved time-division multiplexor with phase-compensated frequency doublers
Assignee: Avago Technologies International Sales Pte Ltd
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Filing: 1990-08-24
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Granted: 1992-05-05
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Expires: 2010-08-24
Abstract
Abstract A synchronous, interleaved, time-division M:1 multiplexor. Following an input stage of parallel synchronous latches for latching M incoming parallel data bits (where M is an integer power of two equal to or greater than four) is an intermediate stage of parallel synchronous latches. The intermediate latches are clocked with selected phases of an M-phase clock having M equally-spaced phases of a clock signal having a frequency of B/M (where B is the outgoing bit rate) to latch each bit at a time at least 2/B (i.e., two outgoing bit periods) after such bit is received from its respective input latch. A first stage of 2:1 multiplexors, following the intermediate latches and used to begin multiplexing the latched bits, are clocked with selected phases of the M-phase clock to begin multiplexing each bit at a time at least 1/B (i.e., one outgoing bit period) after such bit is received from its respective intermediate latch. Further stages of 2:1 multiplexors complete the multiplexing and are each clocked with clock signals which are successively doubled in frequency at each additional stage of 2:1 multiplexors (e.g., 2B/M, 4B/M, 8B/M, . . . ) and phase compensated so as to align the clock signals with their respective data. The phase-compensated, frequency doubling for each 2:1 multiplexor stage is done by "exclusive-ORing" pairs of quadrature clock signals from the immediately preceding 2:1 multiplexor stage.
Inventors
- 👤 Kevin J. Negus
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 18:56
CPC Classifications
H; H04; H04J; H04J3/00; H04J3/02; H04J3/04; H04J3/047
Claims Analysis
Total Claims: 45
Claim 1
Independent Claim
212 words
A synchronous, interleaved, time-division M:1 multiplexor for multiplexing M parallel input bits into a serial output bit stream having an output bit rate of B, wherein M is an integer power of two and equal to or greater than four, comprising: first phase-controlled latching means for receiving and latching the M parallel bits in respective synchronization with a first plurality of selected phases of a multiphase clock signal having a frequency of B/M, wherein each of the first plurality of the multiphase clock signal phases is selected to cause the latching of a corresponding received bit to occur substantially at a time at least 2/B after the bit is first received; first interleaver means for receiving and interleaving selected pairs of the M latched bits in respective synchronization with a second plurality of selected phases of the multiphase clock signal, wherein each of the second plurality of the multiphase clock signal phases is selected to cause the interleaving of each bit of a corresponding, selected pair of bits to occur substantially at a time at least 1/B after the bit is first received; and second interleaver means for receiving and interleaving selected dyads of the interleaved pairs of bits in respective synchronization with an interleaver clock signal having a frequency of 2B/M.
Claim 2
Dependent Claim
212 words
A synchronous, interleaved, time-division M:1 multiplexor for multiplexing M parallel input bits into a serial output bit stream having an output bit rate of B, wherein M is an integer power of two and equal to or greater than four, comprising: first phase-controlled latching means for receiving and latching the M parallel bits in respective synchronization with a first plurality of selected phases of a multiphase clock signal having a frequency of B/M, wherein each of the first plurality of the multiphase clock signal phases is selected to cause the latching of a corresponding received bit to occur substantially at a time at least 2/B after the bit is first received; first interleaver means for receiving and interleaving selected pairs of the M latched bits in respective synchronization with a second plurality of selected phases of the multiphase clock signal, wherein each of the second plurality of the multiphase clock signal phases is selected to cause the interleaving of each bit of a corresponding, selected pair of bits to occur substantially at a time at least 1/B after the bit is first received; and second interleaver means for receiving and interleaving selected dyads of the interleaved pairs of bits in respective synchronization with an interleaver clock signal having a frequency of 2B/M.
Claim 3
Dependent Claim
125 words
A multiplexor according to claim 1 further comprising second phase-controlled latching means for receiving and further latching the M latched bits in respective synchronization with a third plurality of selected phases of the multiphase clock signal, wherein each of the third plurality of the multiphase clock signal phases is selected to cause the latching of a corresponding received bit to occur substantially at a time at least 2/B after the bit is first received, and further wherein each of the second plurality of selected multiphase clock signal phases for the first interleaver means is further selected to cause the interleaving of each bit of the respective, selected pairs of bits to occur substantially at a time at least 2/B after the bit is first received.
Claim 4
Dependent Claim
46 words
A multiplexor according to claim 1 further comprising input latching means for receiving and latching a plurality of parallel bits in synchronization with at least one selected phase of the multiphase clock signal, and for providing the M parallel bits to the first phase-controlled latching means.
Claim 5
Dependent Claim
29 words
A multiplexor according to claim 1 further comprising multiphase clock generator means for receiving a reference clock signal having a frequency of B and generating the multiphase clock signal.
Claim 6
Dependent Claim
24 words
A multiplexor according to claim 1 further comprising interleaver clock generator means for receiving a reference clock signal and generating the interleaver clock signal.
Claim 7
Dependent Claim
73 words
A multiplexor according to claim 1, wherein the first phase-controlled latching means comprises M D-type flip-flops, wherein each of the flip-flops has a D-input, a clock input and a Q-output, and further wherein each of the D-inputs receives one of the M parallel bits, each of the clock inputs receives one of the first plurality of selected multiphase clock signal phases, and each of the Q-outputs provides one of the M latched bits.
Claim 8
Dependent Claim
79 words
A multiplexor according to claim 1, wherein the first interleaver means comprises M/2 2:1 multiplexors, wherein each of the 2:1 multiplexors has a pair of data inputs, a clock input and a data output, and further wherein each of the pairs of data inputs receives one of the selected pairs of the M latched bits, the clock input receives one of the second plurality of selected multiphase clock signal phases, and the output provides the interleaved pairs of bits.
Claim 9
Dependent Claim
66 words
A multiplexor according to claim 1, wherein the second interleaver means comprises M/4 2:1 multiplexors, wherein each of the 2:1 multiplexors has a pair of data inputs, a clock input and a data output, and further wherein each of the pairs of data inputs receives one of the selected dyads, the clock input receives the interleaver clock signal, and the output provides the interleaved selected dyads.
Claim 10
Dependent Claim
74 words
A multiplexor according to claim 2, wherein the second phase-controlled latching means comprises M D-type flip-flops, wherein each of the flip-flops has a D-input, a clock input and a Q-output, and further wherein each of the D-inputs receives one of the M latched bits, each of the clock inputs receives one of the third plurality of selected multiphase clock signal phases, and each of the Q-outputs provides one of the M further latched bits.
Claim 11
Dependent Claim
74 words
A multiplexor according to claim 3, wherein the input latching means comprises a plurality of D-type flip-flops, wherein each of the flip-flops has a D-input, a clock input and a Q-output, and further wherein each of the D-inputs receives one of the plurality of parallel bits, each of the clock inputs receives one selected phase of the multiphase clock signal, and each of M of the Q-outputs provides one of the M parallel bits.
Claim 12
Dependent Claim
29 words
A multiplexor according to claim 4, wherein the multiphase clock generator means comprises a plurality of D-type flip-flops coupled to receive and frequency-divide the reference clock signal by M.
Claim 13
Dependent Claim
35 words
A multiplexor according to claim 5, wherein the interleaver clock generator means comprises a signal delay line having an input which receives the reference clock signal and an output which provides the interleaver clock signal.
Claim 14
Dependent Claim
192 words
A synchronous, interleaved, time-division M:1 multiplexor for multiplexing M parallel input bits into a serial output bit stream having an output bit rate of B, wherein M is an integer power of two and equal to or greater than four, comprising: first interleaver means for receiving and interleaving selected pairs of the M parallel input bits in respective synchronization with a first plurality of selected phases of a multiphase clock signal having a frequency of B/M, wherein each of the first plurality of the multiphase clock signal phases is selected to cause the interleaving of each bit of a corresponding, selected pair of bits to occur substantially at a time at least 1/B after the bit is first received; second interleaver means for receiving and interleaving selected dyads of the interleaved pairs of bits in respective synchronization with an interleaver clock signal having a frequency of 2B/M; and interleaver clock generator means for generating the interleaver clock signal in synchronization with at least one of a second plurality of selected phases of the multiphase clock signal, wherein the interleaver clock signal becomes active substantially simultaneously as the selected dyads are first received.
Claim 15
Dependent Claim
192 words
A synchronous, interleaved, time-division M:1 multiplexor for multiplexing M parallel input bits into a serial output bit stream having an output bit rate of B, wherein M is an integer power of two and equal to or greater than four, comprising: first interleaver means for receiving and interleaving selected pairs of the M parallel input bits in respective synchronization with a first plurality of selected phases of a multiphase clock signal having a frequency of B/M, wherein each of the first plurality of the multiphase clock signal phases is selected to cause the interleaving of each bit of a corresponding, selected pair of bits to occur substantially at a time at least 1/B after the bit is first received; second interleaver means for receiving and interleaving selected dyads of the interleaved pairs of bits in respective synchronization with an interleaver clock signal having a frequency of 2B/M; and interleaver clock generator means for generating the interleaver clock signal in synchronization with at least one of a second plurality of selected phases of the multiphase clock signal, wherein the interleaver clock signal becomes active substantially simultaneously as the selected dyads are first received.
Claim 16
Dependent Claim
46 words
A multiplexor according to claim 13 further comprising phase-controlled latching means for receiving and latching a plurality of parallel bits in synchronization with a third plurality of selected phases of the multiphase clock signal, and for providing the M parallel bits to the first interleaver means.
Claim 17
Dependent Claim
29 words
A multiplexor according to claim 13 further comprising multiphase clock generator means for receiving a reference clock signal having a frequency of B and generating the multiphase clock signal.
Claim 18
Dependent Claim
78 words
A multiplexor according to claim 13, wherein the first interleaver means comprises M/2 2:1 multiplexors, where each of the 2:1 multiplexors has a pair of data inputs, a clock input and a data output, and further wherein each of the pairs of data inputs receives one of the selected pairs of M parallel bits, the clock input receives one of the first plurality of selected multiphase clock signal phases, and the output provides the interleaved pairs of bits.
Claim 19
Dependent Claim
66 words
A multiplexor according to claim 13, wherein the second interleaver means comprises M/4 2:1 multiplexors, wherein each of the 2:1 multiplexors has a pair of data inputs, a clock input and a data output, and further wherein each of the pairs of data inputs receives one of the selected dyads, the clock input receives the interleaver clock signal, and the output provides the interleaved selected dyads.
Claim 20
Dependent Claim
233 words
A synchronous, interleaved, time-division M:1 multiplexor for multiplexing M parallel input bits into a serial output bit stream having an output bit rate of B, wherein M is an integer power of two and equal to or greater than four, comprising: first interleaver means for receiving and interleaving selected pairs of the M parallel input bits in respective synchronization with a plurality of selected phases of a multiphase clock signal having a frequency of B/M, wherein each of the plurality of the multiphase clock signal phases is selected to cause the interleaving of each bit of a corresponding, selected pair of bits to occur substantially at a time at least 1/B after the bit is first received; second interleaver means for receiving and interleaving selected dyads of the interleaved pairs of bits in respective synchronization with an interleaver clock signal having a frequency of 2B/M; and interleaver clock generator means for generating the interleaver clock signal in synchronization with the multiphase clock signal, wherein the interleaver clock signal becomes active substantially simultaneously as the selected dyads are first received, and further wherein the interleaver clock generator means and comprising the further step of further selecting the second plurality of selected multiphase clock signal phases to cause the interleaving of each bit of the respective, selected pair of bits to occur substantially at a time at least 2/B after the bit is first received.
Claim 21
Dependent Claim
233 words
A synchronous, interleaved, time-division M:1 multiplexor for multiplexing M parallel input bits into a serial output bit stream having an output bit rate of B, wherein M is an integer power of two and equal to or greater than four, comprising: first interleaver means for receiving and interleaving selected pairs of the M parallel input bits in respective synchronization with a plurality of selected phases of a multiphase clock signal having a frequency of B/M, wherein each of the plurality of the multiphase clock signal phases is selected to cause the interleaving of each bit of a corresponding, selected pair of bits to occur substantially at a time at least 1/B after the bit is first received; second interleaver means for receiving and interleaving selected dyads of the interleaved pairs of bits in respective synchronization with an interleaver clock signal having a frequency of 2B/M; and interleaver clock generator means for generating the interleaver clock signal in synchronization with the multiphase clock signal, wherein the interleaver clock signal becomes active substantially simultaneously as the selected dyads are first received, and further wherein the interleaver clock generator means and comprising the further step of further selecting the second plurality of selected multiphase clock signal phases to cause the interleaving of each bit of the respective, selected pair of bits to occur substantially at a time at least 2/B after the bit is first received.
Claim 22
Dependent Claim
79 words
A multiplexor according to claim 14, wherein the phase-controlled latching means comprises a plurality of D-type flip-flops, wherein each of the flip-flops has a D-input, a clock input and a Q-output, and further wherein each of the D-inputs receives one of the plurality of parallel bits, each of the clock inputs receives one of the third plurality of selected phases of the multiphase clock signal, and each of M of the Q-outputs provides one of the M parallel bits.
Claim 23
Dependent Claim
29 words
A multiplexor according to claim 15, wherein the multiphase clock generator means comprises a plurality of D-type flip-flops coupled to receive and frequency-divide the reference clock signal by M.
Claim 24
Dependent Claim
244 words
A synchronous, interleaved, time-division M:1 multiplexor for multiplexing M parallel input bits into a serial output bit stream having an output bit rate of B, wherein M is an integer power of two and equal to or greater than four, comprising: first phase-controlled latching means for receiving and latching the M parallel input bits in respective synchronization with a first plurality of selected phases of a multiphase clock signal having a frequency of B/M, wherein each of the first plurality of the multiphase clock signal phases is selected to cause the latching of a corresponding received bit to occur at a time at least 2/B after the bit is first received; first interleaver means for receiving and interleaving selected pairs of the M latched bits in respective synchronization with a second plurality of selected phases of the multiphase clock signal, wherein each of the second plurality of the multiphase clock signal phases is selected to cause the interleaving of each bit of a corresponding, selected pair of bits to occur at a time at least 1/B after the bit is first received; second interleaver means for receiving and interleaving selected dyads of the interleaved pairs of bits in respective synchronization with an interleaver clock signal having a frequency of 2/M; and interleaver clock generator means for generating the interleaver clock signal in synchronization with the multiphase clock signal, wherein the interleaver clock signal becomes active substantially simultaneously as the selected dyads are first received.
Claim 25
Dependent Claim
244 words
A synchronous, interleaved, time-division M:1 multiplexor for multiplexing M parallel input bits into a serial output bit stream having an output bit rate of B, wherein M is an integer power of two and equal to or greater than four, comprising: first phase-controlled latching means for receiving and latching the M parallel input bits in respective synchronization with a first plurality of selected phases of a multiphase clock signal having a frequency of B/M, wherein each of the first plurality of the multiphase clock signal phases is selected to cause the latching of a corresponding received bit to occur at a time at least 2/B after the bit is first received; first interleaver means for receiving and interleaving selected pairs of the M latched bits in respective synchronization with a second plurality of selected phases of the multiphase clock signal, wherein each of the second plurality of the multiphase clock signal phases is selected to cause the interleaving of each bit of a corresponding, selected pair of bits to occur at a time at least 1/B after the bit is first received; second interleaver means for receiving and interleaving selected dyads of the interleaved pairs of bits in respective synchronization with an interleaver clock signal having a frequency of 2/M; and interleaver clock generator means for generating the interleaver clock signal in synchronization with the multiphase clock signal, wherein the interleaver clock signal becomes active substantially simultaneously as the selected dyads are first received.
Claim 26
Dependent Claim
125 words
A multiplexor according to claim 21 further comprising second phase-controlled latching means for receiving and further latching the M latched bits in respective synchronization with a third plurality of selected phases of the multiphase clock signal, wherein each of the third plurality of the multiphase clock signal phases is selected to cause the latching of a corresponding received bit to occur substantially at a time at least 2/B after the bit is first received, and further wherein each of the second plurality of selected multiphase clock signal phases for the first interleaver means is further selected to cause the interleaving of each bit of the respective, selected pairs of bits to occur substantially at a time at least 2/B after the bit is first received.
Claim 27
Dependent Claim
46 words
A multiplexor according to claim 21 further comprising input latching means for receiving and latching a plurality of parallel bits in synchronization with at least one selected phase of the multiphase clock signal, and for providing the M parallel bits to the first phase-controlled latching means.
Claim 28
Dependent Claim
29 words
A multiplexor according to claim 21 further comprising multiphase clock generator means for receiving a reference clock signal having a frequency of B and generating the multiphase clock signal.
Claim 29
Dependent Claim
73 words
A multiplexor according to claim 21, wherein the first phase-controlled latching means comprises M D-type flip-flops, wherein each of the flip-flops has a D-input, a clock input and a Q-output, and further wherein each of the D-inputs receives one of the M parallel bits, each of the clock inputs receives one of the first plurality of selected multiphase clock signal phases, and each of the Q-outputs provides one of the M latched bits.
Claim 30
Dependent Claim
79 words
A multiplexor according to claim 21, wherein the first interleaver means comprises M/2 2:1 multiplexors, wherein each of the 2:1 multiplexors has a pair of data inputs, a clock input and a data output, and further wherein each of the pairs of data inputs receives one of the selected pairs of the M latched bits, the clock input receives one of the second plurality of selected multiphase clock signal phases, and the output provides the interleaved pairs of bits.
Claim 31
Dependent Claim
66 words
A multiplexor according to claim 21, wherein the second interleaver means comprises M/4 2:1 multiplexors, wherein each of the 2:1 multiplexors has a pair of data inputs, a clock input and a data output, and further wherein each of the pairs of data inputs receives one of the selected dyads, the clock input receives the interleaver clock signal, and the output provides the interleaved selected dyads.
Claim 32
Dependent Claim
39 words
A multiplexor according to claim 21, wherein the interleaver clock generator means comprises an exclusive-OR gate coupled to receive the second plurality of selected phases of the multiphase clock signal and provide the interleaver clock signal in synchronization therewith.
Claim 33
Dependent Claim
30 words
A multiplexor according to claim 28, wherein the plurality of selected phases received by the interleaver clock generator means comprises a pair of quadrature phases of the multiphase clock signal.
Claim 34
Dependent Claim
74 words
A multiplexor according to claim 22, wherein the second phase-controlled latching means comprises M D-type flip-flops, wherein each of the flip-flops has a D-input, a clock input and a Q-output, and further wherein each of the D-inputs receives one of the M latched bits, each of the clock inputs receives one of the third plurality of selected multiphase clock signal phases, and each of the Q-outputs provides one of the M further latched bits.
Claim 35
Dependent Claim
74 words
A multiplexor according to claim 23, wherein the input latching means comprises a plurality of D-type flip-flops, wherein each of the flip-flops has a D-input, a clock input and a Q-output, and further wherein each of the D-inputs receives one of the plurality of parallel bits, each of the clock inputs receives one selected phase of the multiphase clock signal, and each of M of the Q-outputs provides one of the M parallel bits.
Claim 36
Dependent Claim
29 words
A multiplexor according to claim 24, wherein the multiphase clock generator means comprises a plurality of D-type flip-flops coupled to receive and frequency-divide the reference clock signal by M.
Claim 37
Independent Claim
204 words
A method for synchronously interleaving and time-division M:1 multiplexing M parallel input bits into a serial output bit stream having an output bit rate of B, wherein M is an integer power of two and equal to or greater than four, comprising the steps of: receiving and latching the M parallel input bits in respective synchronization with a first plurality of selected phases of a multiphase clock signal having a frequency of B/M, wherein each of the first plurality of the multiphase clock signal phases is selected to cause the latching of a corresponding bit to occur substantially at a time at least 2/B after the respective bit is first received; receiving and interleaving selected pairs of the M latched bits in respective synchronization with a second plurality of selected phases of the multiphase clock signal, wherein each of the second plurality of the multiphase clock signal phases is selected to cause the interleaving of each bit of a corresponding, selected pair of bits to occur substantially at a time at least 1/B after the bit is first received; and receiving and interleaving selected dyads of the interleaved pairs of bits in respective synchronization with an interleaver clock signal having a frequency of 2B/M.
Claim 38
Independent Claim
204 words
A method for synchronously interleaving and time-division M:1 multiplexing M parallel input bits into a serial output bit stream having an output bit rate of B, wherein M is an integer power of two and equal to or greater than four, comprising the steps of: receiving and latching the M parallel input bits in respective synchronization with a first plurality of selected phases of a multiphase clock signal having a frequency of B/M, wherein each of the first plurality of the multiphase clock signal phases is selected to cause the latching of a corresponding bit to occur substantially at a time at least 2/B after the respective bit is first received; receiving and interleaving selected pairs of the M latched bits in respective synchronization with a second plurality of selected phases of the multiphase clock signal, wherein each of the second plurality of the multiphase clock signal phases is selected to cause the interleaving of each bit of a corresponding, selected pair of bits to occur substantially at a time at least 1/B after the bit is first received; and receiving and interleaving selected dyads of the interleaved pairs of bits in respective synchronization with an interleaver clock signal having a frequency of 2B/M.
Claim 39
Dependent Claim
118 words
A method according to claim 33 further comprising the step of receiving and further latching the M latched bits in respective synchronization with a third plurality of selected phases of the multiphase clock signal, wherein each of the third plurality of the multiphase clock signal phases is selected to cause the latching of a corresponding bit to occur substantially at a time at least 2/B after the respective bit is first received, and comprising the further step of further selecting the second plurality of selected multiphase clock signal phases to cause the interleaving of each bit of the respective, selected pair of bits to occur substantially at a time at least 2/B after the bit is first received.
Claim 40
Independent Claim
183 words
A method for synchronously interleaving and time-division M:1 multiplexing M parallel input bits into a serial output bit stream having an output bit rate of B, wherein M is an integer power of two and equal to or greater than four, comprising the steps of: receiving and interleaving selected pairs of the M parallel input bits in respective synchronization with a first plurality of selected phases of a multiphase clock signal having a frequency of B/M, wherein each of the first plurality of the multiphase clock signal phases is selected to cause the interleaving of each bit of a corresponding, selected pair of bits to occur substantially at a time at least 1/B after the bit is first received; receiving and interleaving selected dyads of the interleaved pairs of bits in respective synchronization with an interleaver clock signal having a frequency of 2B/M; and generating the interleaver clock signal in synchronization with at least on of a second plurality of selected phases of the multiphase clock signal, wherein the interleaver clock signal becomes active substantially simultaneously as the selected dyads are first received.
Claim 41
Independent Claim
183 words
A method for synchronously interleaving and time-division M:1 multiplexing M parallel input bits into a serial output bit stream having an output bit rate of B, wherein M is an integer power of two and equal to or greater than four, comprising the steps of: receiving and interleaving selected pairs of the M parallel input bits in respective synchronization with a first plurality of selected phases of a multiphase clock signal having a frequency of B/M, wherein each of the first plurality of the multiphase clock signal phases is selected to cause the interleaving of each bit of a corresponding, selected pair of bits to occur substantially at a time at least 1/B after the bit is first received; receiving and interleaving selected dyads of the interleaved pairs of bits in respective synchronization with an interleaver clock signal having a frequency of 2B/M; and generating the interleaver clock signal in synchronization with at least on of a second plurality of selected phases of the multiphase clock signal, wherein the interleaver clock signal becomes active substantially simultaneously as the selected dyads are first received.
Claim 42
Independent Claim
230 words
A method for synchronously interleaving and time-division M:1 multiplexing M parallel input bits into a serial output bit stream having an output bit rate of B, wherein M is an integer power of two and equal to or greater than four, comprising the steps of: receiving and latching the M parallel input bits in respective synchronization with a first plurality of selected phases of a multiphase clock signal having a frequency of B/M, wherein each of the first plurality of the multiphase clock signal phases is selected to cause the latching of a corresponding bit to occur at a time at least 2/B after the respective bit is first received; receiving and interleaving selected pairs of the M latched bits in respective synchronization with a second plurality of selected phases of the multiphase clock signal, wherein each of the second plurality of the multiphase clock signal phases is selected to cause the interleaving of each bit of a corresponding, selected pair of bits to occur at a time at least 1/B after the bit is first received; receiving and interleaving selected dyads of the interleaved pairs of bits in respective synchronization with an interleaver clock signal having a frequency of 2B/M; and generating the interleaver clock signal in synchronization with the multiphase clock signal, wherein the interleaver clock signal becomes active substantially simultaneously as the selected dyads are first received.
Claim 43
Independent Claim
230 words
A method for synchronously interleaving and time-division M:1 multiplexing M parallel input bits into a serial output bit stream having an output bit rate of B, wherein M is an integer power of two and equal to or greater than four, comprising the steps of: receiving and latching the M parallel input bits in respective synchronization with a first plurality of selected phases of a multiphase clock signal having a frequency of B/M, wherein each of the first plurality of the multiphase clock signal phases is selected to cause the latching of a corresponding bit to occur at a time at least 2/B after the respective bit is first received; receiving and interleaving selected pairs of the M latched bits in respective synchronization with a second plurality of selected phases of the multiphase clock signal, wherein each of the second plurality of the multiphase clock signal phases is selected to cause the interleaving of each bit of a corresponding, selected pair of bits to occur at a time at least 1/B after the bit is first received; receiving and interleaving selected dyads of the interleaved pairs of bits in respective synchronization with an interleaver clock signal having a frequency of 2B/M; and generating the interleaver clock signal in synchronization with the multiphase clock signal, wherein the interleaver clock signal becomes active substantially simultaneously as the selected dyads are first received.
Claim 44
Dependent Claim
118 words
A method according to claim 36 further comprising the step of receiving and further latching the M latched bits in respective synchronization with a third plurality of selected phases of the multiphase clock signal, wherein each of the third plurality of the multiphase clock signal phases is selected to cause the latching of a corresponding bit to occur substantially at a time at least 2/B after the respective bit is first received, and comprising the further step of further selecting the second plurality of selected multiphase clock signal phases to cause the interleaving of each bit of the respective, selected pair of bits to occur substantially at a time at least 2/B after the bit is first received.
Claim 45
Dependent Claim
30 words
A multiplexor according to claim 18, wherein the plurality of selected phases received by the interleaver clock generator means comprises a pair of quadrature phases of the multiphase clock signal.
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