Patent US5840624A successfully refreshed from Google Patents.
US5840624A
Expired / Lapsed
US
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Reduction of via over etching for borderless contacts
Assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Filing: 1996-03-15
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Granted: 1998-11-24
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Expires: 2016-03-15
Abstract
Abstract A method for forming a borderless, contact or via hole, has been developed, in which a thin silicon nitride layer is used as an etch stop to prevent attack of an underlying interlevel dielectric layer, during the opening of the borderless, contact or via hole, in an overlying, interlevel dielectric layer. The thin silicon nitride layer is the top layer of an interlevel dielectric composite layer, used between metal interconnect levels.
Inventors
- 👤 Syun-Ming Jang
- 👤 Yu Chen-Hua Douglas
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 15:31
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/41; H10W20/425; H10P; H10P50/00; H10P50/20; H10P50/28; H10P50/282; H10P50/283; H10W20/01; H10W20/071; H10W20/074; H10W20/081; H10W20/42; H10W20/45; H10W20/48
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
381 words
A method for fabricating a MOSFET device structure, on a semiconductor substrate, using an etch stop layer, as part of an underlying interlevel dielectric composite layer, to prevent the etching of said underlying said interlevel dielectric composite layer, during the creation of a via hole, in an overlying interlevel dielectric layer, comprising the steps of: providing a MOSFET device structure, with source and drain regions on said semiconductor substrate; providing metal filled contact holes, in a silicon oxide layer, contacting a source and drain region of said MOSFET device structure; deposition of a first interlevel dielectric composite layer, consisting of a thick underlying first insulator layer, and of a thin overlying second insulator layer, on said metal filled contact hole, and on a top surface of said silicon oxide layer; opening a first via hole in said first interlevel dielectric composite layer, to said metal filled contact hole; depositing a first metallization layer on said first interlevel dielectric composite layer, completely filling said first via hole; patterning of a top portion of said first metallization layer to form a first level metal structure; deposition of a second interlevel dielectric layer on said first level metal structure, and on a top surface of said thin overlying insulator layer, of said first interlevel dielectric composite layer; opening a second via hole in said second interlevel dielectric layer, to said first level metal structure, and to the top surface of said thin overlying insulator layer, of said first interlevel dielectric composite layer, in regions where said second via hole did not overlie said first level metal structure, exposing a portion of the top surface of said first level metal structure, and exposing a side of said first level metal structure; deposition of a second metallization layer on said second interlevel dielectric layer, completely filling said second via hole, including deposition on top surface of said thin overlying insulator layer, of said first interlevel dielectric composite layer, in said second via hole, in regions where said second via hole did not overlie said first metal structure, deposition on a portion of the top surface of said first level metal structure, and deposition on the exposed side of said first level metal structure; and patterning of said second metallization layer to form second level metal structure.
Claim 2
Independent Claim
381 words
A method for fabricating a MOSFET device structure, on a semiconductor substrate, using an etch stop layer, as part of an underlying interlevel dielectric composite layer, to prevent the etching of said underlying said interlevel dielectric composite layer, during the creation of a via hole, in an overlying interlevel dielectric layer, comprising the steps of: providing a MOSFET device structure, with source and drain regions on said semiconductor substrate; providing metal filled contact holes, in a silicon oxide layer, contacting a source and drain region of said MOSFET device structure; deposition of a first interlevel dielectric composite layer, consisting of a thick underlying first insulator layer, and of a thin overlying second insulator layer, on said metal filled contact hole, and on a top surface of said silicon oxide layer; opening a first via hole in said first interlevel dielectric composite layer, to said metal filled contact hole; depositing a first metallization layer on said first interlevel dielectric composite layer, completely filling said first via hole; patterning of a top portion of said first metallization layer to form a first level metal structure; deposition of a second interlevel dielectric layer on said first level metal structure, and on a top surface of said thin overlying insulator layer, of said first interlevel dielectric composite layer; opening a second via hole in said second interlevel dielectric layer, to said first level metal structure, and to the top surface of said thin overlying insulator layer, of said first interlevel dielectric composite layer, in regions where said second via hole did not overlie said first level metal structure, exposing a portion of the top surface of said first level metal structure, and exposing a side of said first level metal structure; deposition of a second metallization layer on said second interlevel dielectric layer, completely filling said second via hole, including deposition on top surface of said thin overlying insulator layer, of said first interlevel dielectric composite layer, in said second via hole, in regions where said second via hole did not overlie said first metal structure, deposition on a portion of the top surface of said first level metal structure, and deposition on the exposed side of said first level metal structure; and patterning of said second metallization layer to form second level metal structure.
Claim 3
Dependent Claim
43 words
The method of claim 1, wherein said thick underlying insulator layer, of said first interlevel dielectric composite layer, is silicon oxide, deposited using PECVD processing, at a temperature between about 400° to 600° C., to a thickness between about 3000 to 6000 Angstroms.
Claim 4
Dependent Claim
43 words
The method of claim 1, wherein said thin overlying insulator layer, of said first interlevel dielectric composite layer, is silicon nitride, deposited using PECVD processing, at a temperature between about 400° to 600° C., to a thickness between about 500 to 1000 Angstroms.
Claim 5
Dependent Claim
47 words
The method of claim 1, wherein said first via hole is formed in said first interlevel dielectric composite layer, via RIE processing, using Cl 2 as an etchant for said thin overlying insulator layer, and using CHF 3 as an etchant for said thick underlying insulator layer.
Claim 6
Dependent Claim
77 words
The method of claim 1, wherein said first metallization layer is deposited using r.f. sputtering, and is comprised of: an underlying layer of titanium nitride, at a thickness between about 200 to 500 Angstroms; a layer of aluminum, containing between about 1 to 3% copper, and between about 0.5 to 1% silicon, at a thickness between about 4000 to 8000 Angstroms; and an overlying layer of titanium nitride, at a thickness between about 200 to 500 Angstroms.
Claim 7
Dependent Claim
23 words
The method of claim 1, wherein said first level metallization structure is formed via anisotropic, RIE procedures, using Cl 2 as an etchant.
Claim 8
Dependent Claim
36 words
The method of claim 1, wherein said second interlevel dielectric layer is silicon oxide, deposited using PECVD processing, at a temperature between about 400° to 600° C., to a thickness between about 3000 to 6000 Angstroms.
Claim 9
Dependent Claim
51 words
The method of claim 1, wherein said second via hole is formed in said second interlevel dielectric layer, via use of RIE procedures, using CHF 3 as an etchant, and with a etch selectivity between said silicon oxide, and an said underlying silicon nitride layer, of between about 3 to 1.
Claim 10
Dependent Claim
77 words
The method of claim 1, wherein said second metallization layer is deposited using r.f. sputtering, and is comprised of: an underlying layer of titanium nitride, at a thickness between about 200 to 500 Angstroms; a layer of aluminum, containing between about 1 to 3% copper, and between about 0.5 to 1% silicon, at a thickness between about 4000 to 8000 Angstroms; and an overlying layer of titanium nitride, at a thickness between about 200 to 500 Angstroms.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-11-23 | 2002-05-25 | 2002-11-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-11-23 | 2006-05-25 | 2006-11-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-11-23 | 2010-05-25 | 2010-11-24 | $7700.00 | Window Closed / Lapsed |