Semiconductor integrated circuit device with multi-level wiring structure

Claim 1

A method of manufacturing a semiconductor integrated circuit device comprising the steps of forming a lower wiring pattern on a field insulating layer formed on a semiconductor substrate; forming entirely an intermediate insulating layer; forming an upper wiring pattern on said intermediate insulating layer; and etching said intermediate insulating layer through a reactive ion etching method of anisotropic etching using said upper and lower wiring patterns as a mask until a surface portion of said field insulating layer is exposed where said upper and lower wiring patterns are absent thereabove, said etching being performed so that side walls made of said intermediate insulating layer remain on both wiring pattern.

Claim 2

A method of manufacturing a semiconductor integrated circuit device comprising the steps of forming a lower wiring pattern on a field insulating layer formed on a semiconductor substrate; forming entirely an intermediate insulating layer; forming an upper wiring pattern on said intermediate insulating layer; and etching said intermediate insulating layer through a reactive ion etching method of anisotropic etching using said upper and lower wiring patterns as a mask until a surface portion of said field insulating layer is exposed where said upper and lower wiring patterns are absent thereabove, said etching being performed so that side walls made of said intermediate insulating layer remain on both wiring pattern.

Claim 4

A method of manufacturing a semiconductor integrated circuit device, said method comprising the steps of forming a lower wiring pattern on a field insulating layer which has a thickness and is formed on a semiconductor substrate; forming entirely an intermediate insulating layer; forming an upper wiring pattern on said intermediate insulating layer; and etching said intermediate insulating layer through a reactive ion etching method of anisotropic etching using said upper and lower wiring patterns as a mask until a surface portion of said field insulating layer is exposed where said where said upper and lower wiring patterns are absent thereabove, said etching being continuously performed from said surface portion of said field insulating layer inwardly by a depth which is shallower than said thickness of said field insulating layer so that a concavity having a bottom constituted of said field insulating layer is formed in said field insulating layer from said surface portion thereof.

Claim 5

A method of manufacturing a semiconductor integrated circuit device, said method comprising the steps of forming a lower wiring pattern on a field insulating layer which has a thickness and is formed on a semiconductor substrate; forming entirely an intermediate insulating layer; forming an upper wiring pattern on said intermediate insulating layer; and etching said intermediate insulating layer through a reactive ion etching method of anisotropic etching using said upper and lower wiring patterns as a mask until a surface portion of said field insulating layer is exposed where said where said upper and lower wiring patterns are absent thereabove, said etching being continuously performed from said surface portion of said field insulating layer inwardly by a depth which is shallower than said thickness of said field insulating layer so that a concavity having a bottom constituted of said field insulating layer is formed in said field insulating layer from said surface portion thereof.