US5587338A
Expired / Lapsed
US
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Polysilicon contact stud process
Assignee: Vanguard International Semiconductor Corp
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Filing: 1995-04-27
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Granted: 1996-12-24
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Expires: 2015-04-27
Abstract
Abstract A process for creating a polysilicon contact stud, to connect overlying metallizations, to underlying active device regions in a semiconductor substrate, has been developed. After filling a contact hole with insitu doped polysilicon, and overlying with a titanium film, an anneal cycle is performed to convert the unwanted portions of polysilicon to titanium silicide. The silicide is then selectively removed, leaving polysilicon only in the contact hole, thus resulting in the desired stud configuration.
Inventors
- 👤 Horng-Huei Tseng
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 22:57
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/056
Claims Analysis
Total Claims: 26
Claim 1
Independent Claim
263 words
A method for fabricating a MOSFET device on a semiconductor substrate, using a conductive stud to provide electrical contact between active device elements in the substrate, and an overlying interconnect metallization, comprising the steps of: providing the active device elements in the said semiconductor substrate; depositing a first dielectric layer on said semiconductor substrate, that includes said active device elements; depositing a second dielectric layer on said first dielectric layer, to form composite dielectric layer; photolithographic processing to open a region in a photoresist layer, exposing an area of said composite dielectric layer, directly overlying said active device element; anisotropic removal of said composite dielectric layer, in said exposed region of said photoresist layer, to create contact hole opening to said active device element; cleaning the surface of said active device element, in said contact hole opening; depositing an insitu doped polysilicon layer on the surface of said active device element, in said contact hole opening, and on the surface of said second dielectric layer; depositing a layer of titanium on said insitu doped polysilicon layer; annealing to completely convert a portion of said insitu doped polysilicon layer to a titanium silicide layer, on the surface of said second dielectric layer, while converting only a top portion of said insitu doped polysilicon layer, in said contact hole opening, to titanium silicide; removal of said titanium silicide from the surface of said second dielectric layer, and from the surface of said unconverted insitu doped polysilicon, in said contact hole; and removal of said second dielectric layer from the surface of said first dielectric layer.
Claim 2
Independent Claim
263 words
A method for fabricating a MOSFET device on a semiconductor substrate, using a conductive stud to provide electrical contact between active device elements in the substrate, and an overlying interconnect metallization, comprising the steps of: providing the active device elements in the said semiconductor substrate; depositing a first dielectric layer on said semiconductor substrate, that includes said active device elements; depositing a second dielectric layer on said first dielectric layer, to form composite dielectric layer; photolithographic processing to open a region in a photoresist layer, exposing an area of said composite dielectric layer, directly overlying said active device element; anisotropic removal of said composite dielectric layer, in said exposed region of said photoresist layer, to create contact hole opening to said active device element; cleaning the surface of said active device element, in said contact hole opening; depositing an insitu doped polysilicon layer on the surface of said active device element, in said contact hole opening, and on the surface of said second dielectric layer; depositing a layer of titanium on said insitu doped polysilicon layer; annealing to completely convert a portion of said insitu doped polysilicon layer to a titanium silicide layer, on the surface of said second dielectric layer, while converting only a top portion of said insitu doped polysilicon layer, in said contact hole opening, to titanium silicide; removal of said titanium silicide from the surface of said second dielectric layer, and from the surface of said unconverted insitu doped polysilicon, in said contact hole; and removal of said second dielectric layer from the surface of said first dielectric layer.
Claim 3
Dependent Claim
20 words
The method of claim 1, wherein said active device elements, in said semiconductor substrate, are N type doped diffusion regions.
Claim 4
Dependent Claim
36 words
The method of claim 1, wherein said first dielectric layer is silicon oxide, deposited using LPCVD processing, at a temperature between about 400° C. to 800° C., to a thickness between about 6000 to 12000 Angstroms.
Claim 5
Dependent Claim
34 words
The method of claim 1, wherein second dielectric layer is silicon nitride, deposited using LPCVD processing, at a temperature between about 600° to 800° C., to a thickness between about 500 to 3000 Angstroms.
Claim 6
Dependent Claim
43 words
The method of claim 1, wherein said contact hole is created using anisotropic RIE removal of said composite dielectric layer, using Cl 2 , for said second dielectric layer, and a CF 4 -CHF 3 - Argon chemistry, for said first dielectric layer.
Claim 7
Dependent Claim
46 words
The method of claim 1, wherein surface of said active device element, in said contact hole opening, is cleaned using a solution of ammonium fluoride, and hydrofluoric acid, at a temperature between about 20° to 25° C., for a time between about 10 to 60 sec.
Claim 8
Dependent Claim
60 words
The method of claim 1, wherein said insitu doped polysilicon layer is deposited using LPCVD processing, at a temperature between about 500° to 700° C,. to a thickness between about 1000 to 3000 Angsttoms, using a flow between about 1200 to 1400 sccm of SiH 4 , and a flow between about 100 to 300 sccm of PH 3 .
Claim 9
Dependent Claim
22 words
The method of claim 1, wherein the sheet resistance of said insitu doped polysilicon layer is between about 10 to 110 ohms/square.
Claim 10
Dependent Claim
23 words
The method of claim 1, wherein said titanium layer is deposited using rf sputtering, to a thickness between about 500 to 2000 Angsttoms.
Claim 11
Dependent Claim
42 words
The method of claim 1, wherein said annealing is performed, using a furnace, at a temperature between about 400° to 600° C., for a time needed to convert between about 1000 to 2000 Angstroms of said insitu doped polysilicon to titanium silicide.
Claim 12
Dependent Claim
23 words
The method of claim 1, wherein said titanium silicide is removed using hydrofluoric acid, at a temperature between about 20° to 25° C.
Claim 13
Dependent Claim
14 words
The method of claim 1, wherein silicon nitride is removed using hot phosphoric acid.
Claim 14
Independent Claim
258 words
A method of fabricating a MOSFET device on a semiconductor substrate, using a polysilicon contact stud to provide electrical contact between a source and drain device region in a substrate, and an overlying interconnect metallization, comprising the steps of: providing said source and drain region in said semiconductor substrate; depositing a silicon oxide layer on said semiconductor substrate, that includes said source and drain region; depositing a silicon nitride layer on said silicon oxide layer, to form a composite dielectric layer; photolithographic processing to open a region in a photoresist layer, exposing said composite dielectric layer, directly overlying said source and drain region; anisotropic removal of said composite dielectric layer, in said exposed region in said photoresist layer, to create contact hole to said source and drain region; cleaning the surface of said source and drain region, in said contact hole opening; depositing an insitu doped polysilicon layer on said source and drain region, in said contact hole opening, and on said silicon nitride layer; depositing a titanium layer on said insitu doped polysilicon layer; annealing to completely convert said insitu doped polysilicon layer, to titanium silicide, on the surface of said silicon nitride layer, while converting only a top portion of said insitu doped polysilicon, in said contact hole opening, to titanium silicide; removal of said titanium silicide from the surface of said silicon nitride layer, and from the top surface of said unconverted insitu doped polysilicon, in said contact hole opening; and removal of said silicon nitride layer from the surface of said silicon oxide layer.
Claim 15
Independent Claim
258 words
A method of fabricating a MOSFET device on a semiconductor substrate, using a polysilicon contact stud to provide electrical contact between a source and drain device region in a substrate, and an overlying interconnect metallization, comprising the steps of: providing said source and drain region in said semiconductor substrate; depositing a silicon oxide layer on said semiconductor substrate, that includes said source and drain region; depositing a silicon nitride layer on said silicon oxide layer, to form a composite dielectric layer; photolithographic processing to open a region in a photoresist layer, exposing said composite dielectric layer, directly overlying said source and drain region; anisotropic removal of said composite dielectric layer, in said exposed region in said photoresist layer, to create contact hole to said source and drain region; cleaning the surface of said source and drain region, in said contact hole opening; depositing an insitu doped polysilicon layer on said source and drain region, in said contact hole opening, and on said silicon nitride layer; depositing a titanium layer on said insitu doped polysilicon layer; annealing to completely convert said insitu doped polysilicon layer, to titanium silicide, on the surface of said silicon nitride layer, while converting only a top portion of said insitu doped polysilicon, in said contact hole opening, to titanium silicide; removal of said titanium silicide from the surface of said silicon nitride layer, and from the top surface of said unconverted insitu doped polysilicon, in said contact hole opening; and removal of said silicon nitride layer from the surface of said silicon oxide layer.
Claim 16
Dependent Claim
21 words
The method of claim 13, wherein said source and drain region in said semiconductor substrate, is an N type doped region.
Claim 17
Dependent Claim
33 words
The method of claim 13, wherein said silicon oxide layer is grown using LPCVD processing, at a temperature between about 400° to 800° C., to a thickness between about 6000 to 12000 Angstroms.
Claim 18
Dependent Claim
33 words
The method of claim 13, wherein said silicon nitride layer is grown using LPCVD processing, at a temperature between about 600° to 800° C., to a thickness between about 500 to 3000 Angstroms.
Claim 19
Dependent Claim
42 words
The method of claim 13, wherein said contact hole, to said source and drain region, is created via RIE processing using Cl 2 , for said silicon nitride layer, and a CF 4 -CHF 3 -Argon chemistry, for said silicon oxide layer.
Claim 20
Dependent Claim
46 words
The method of claim 13, wherein surface of said source and drain, in said contact hole opening, is cleaned using a solution of ammonium fluoride, and hydrofluoric acid, at a temperature between about 20° to 25° C., for a time between about 10 to 60 sec.
Claim 21
Dependent Claim
61 words
The method of claim 13, wherein said insitu doped polysilicon layer, used to create the polysilicon contact stud, is deposited using LPCVD processing, at a temperature between about 500° to 700° C., to a thickness between about 1000 to 3000 Angstroms, using a SiH4 flow between about 1200 to 1400 sccm, and a PH3 flow between about 100 to 300 sccm.
Claim 22
Dependent Claim
29 words
The method of claim 13, wherein the sheet resistance of said insitu doped polysilicon layer, used to create said polysilicon contact stud, is between about 10 to 110 ohms/square.
Claim 23
Dependent Claim
23 words
The method of claim 13, wherein said titanium layer is deposited using rf sputtering, to a thickness between about 500 to 2000 Angstroms.
Claim 24
Dependent Claim
46 words
The method of claim 13, wherein said annealing is performed, using a furnace process, at a temperature between about 400° to 600° C., for a specific amount of time needed to convert between about 1000 to 2000 Angstroms of said insitu doped polysilicon to titanium silicide.
Claim 25
Dependent Claim
23 words
The method of claim 13, wherein said titanium silicide is removed using hydrofluoric acid, at a temperature between about 20° to 25° C.
Claim 26
Dependent Claim
16 words
The method of claim 13, wherein said silicon nitride layer is removed using hot phosphoric acid.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-12-24 | 2000-06-24 | 2000-12-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-12-24 | 2004-06-24 | 2004-12-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-12-24 | 2008-06-24 | 2008-12-24 | $7700.00 | Window Closed / Lapsed |