US5196373A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of making trench conductor and crossunder architecture
Assignee: Intersil Corp
•
Filing: 1991-07-31
•
Granted: 1993-03-23
•
Expires: 2011-07-31
Abstract
Abstract The trench pattern of a dielectrically isolated island architecture is filled with doped polysilicon and used as an interconnect structure for circuit devices that are supported within the islands, thereby decreasing the amount of topside interconnect and reducing the potential for parasitics beneath tracks of surface metal. The trench pattern may serve as a voltage distribution network or provide crossunders beneath surface tracks. In addition, at least one of the islands may contain one or more auxiliary poly-filled trench regions to perform the crossunder function. Such an auxiliary trench region may be also provided in an island that contains a circuit device. Manufacture of the conductor-filled trench structure may be faciliated by depositing polysilicon over a dielectrically coated trench grid structure and then planarizing the polysilicon to the surface of the oxide dielectric. The exposed polysilicon is doped and then oxidized to seal the dopant, which forms a thin oxide layer on the poly. The oxide dielectric for the trench can then be selectively patterned to form a mask to be for the initial doping of the islands.
Inventors
- 👤 James D. Beasom
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 02:14
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/41; H10W20/43; H10W20/432; H10W20/20; H10W20/44; H10W20/4451; H10W72/00; Y; Y10; Y10S; Y10S148/00; Y10S148/02; Y10S148/15
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
188 words
A method of manufacturing a semiconductor device comprising the steps of: (a) forming a trench pattern in a semiconductor layer that is electrically isolated from an underlying substrate, so as to subdivide said semiconductor layer into a plurality of spaced-apart, electrically isolated islands; (b) forming dielectric material on top surfaces of said islands, and upon sidewalls of said trench pattern; (c) forming electrically conductive interconnect material in said trench pattern; and (d) forming a first aperture in dielectric material that has been formed on the top surface of an island, such that said first aperture extends from a first island location to a first portion of said electrically conductive interconnect material in said trench pattern, and forming a second aperture in dielectric material that has been formed on the top surface of an island, such that said second aperture extends from a second island location to a second portion of said electrically conductive interconnect material in said trench pattern; and (e) conductively connecting first and second island locations to said first and second portions of the electrical interconnect material formed in said first portion of said trench pattern.
Claim 2
Independent Claim
188 words
A method of manufacturing a semiconductor device comprising the steps of: (a) forming a trench pattern in a semiconductor layer that is electrically isolated from an underlying substrate, so as to subdivide said semiconductor layer into a plurality of spaced-apart, electrically isolated islands; (b) forming dielectric material on top surfaces of said islands, and upon sidewalls of said trench pattern; (c) forming electrically conductive interconnect material in said trench pattern; and (d) forming a first aperture in dielectric material that has been formed on the top surface of an island, such that said first aperture extends from a first island location to a first portion of said electrically conductive interconnect material in said trench pattern, and forming a second aperture in dielectric material that has been formed on the top surface of an island, such that said second aperture extends from a second island location to a second portion of said electrically conductive interconnect material in said trench pattern; and (e) conductively connecting first and second island locations to said first and second portions of the electrical interconnect material formed in said first portion of said trench pattern.
Claim 3
Dependent Claim
41 words
A method according to claim 1, wherein step (a) comprises forming a trench pattern in a semiconductor layer that is dielectrically isolated from an underlying substrate, so as to subdivide said semiconductor layer into a plurality of spaced-apart, dielectrically isolated islands.
Claim 4
Dependent Claim
20 words
A method according to claim 1, wherein said semiconductor layer comprises silicon and said electrically conductive interconnect material comprises polysilicon.
Claim 5
Dependent Claim
16 words
A method according to claim 3, wherein said electrically conductive interconnect material includes a refractory metal.
Claim 6
Dependent Claim
61 words
A method according to claim 1, wherein step (c) comprises non-selectively depositing a layer of electrically conductive interconnect material on said trench pattern and on the dielectric material that has been formed on top surfaces of islands, and planarizing said layer of electrically conductive interconnect material down to the dielectric material that has been formed on top surfaces of said islands.
Claim 7
Dependent Claim
24 words
A method according to claim 5, wherein said layer of electrically conductive interconnect material comprises polysilicon and further including doping said layer of polysilicon.
Claim 8
Dependent Claim
81 words
A method according to claim 6, wherein step (d) further includes forming a third aperture in dielectric material that has been formed on the top surface of an island, such said third aperture exposes a surface portion of an island where a semiconductor region is to be formed, and further including doping said surface portion of said island during doping said layer of polysilicon, so as to form doped a semiconductor region in an island region exposed by said third aperture.
Claim 9
Dependent Claim
75 words
A method according to claim 1, wherein step (d) further includes forming a third aperture in dielectric material that has been formed on the top surface of an island, such said third aperture exposes a surface portion of an island where a semiconductor region is to be formed, and further including doping said surface portion of said island, so as to form doped a semiconductor region in an island region exposed by said third aperture.
Claim 10
Independent Claim
101 words
A method of manufacturing a semiconductor device comprising the steps of: (a) forming a trench pattern in a semiconductor layer that is electrically isolated from an underlying substrate, so as to subdivide said semiconductor layer into a plurality of spaced-apart, electrically isolated islands, and an auxiliary trench region in a selected portion of said semiconductor layer spaced apart from said trench pattern; (b) forming dielectric material on top surfaces of said semiconductor layer, and upon sidewalls of said trench pattern and said auxiliary trench region; and (c) forming electrically conductive interconnect material in said trench pattern and said auxiliary trench region.
Claim 11
Independent Claim
101 words
A method of manufacturing a semiconductor device comprising the steps of: (a) forming a trench pattern in a semiconductor layer that is electrically isolated from an underlying substrate, so as to subdivide said semiconductor layer into a plurality of spaced-apart, electrically isolated islands, and an auxiliary trench region in a selected portion of said semiconductor layer spaced apart from said trench pattern; (b) forming dielectric material on top surfaces of said semiconductor layer, and upon sidewalls of said trench pattern and said auxiliary trench region; and (c) forming electrically conductive interconnect material in said trench pattern and said auxiliary trench region.
Claim 12
Dependent Claim
72 words
A method according to claim 9, further comprising the step of (d) forming a first conductive layer overlying dielectric material atop the surface of said auxiliary trench region between first and second locations of electrically conductive material in said auxiliary trench region, and providing respective electrical connections between second and third conductive layers overlying said dielectric material and said first and second locations of electrically conductive material in said auxiliary trench region.
Claim 13
Dependent Claim
22 words
A method according to claim 10, wherein said semiconductor layer comprises silicon and said electrically conductive material includes doped or undoped polysilicon.
Claim 14
Dependent Claim
14 words
A method according to claim 11, wherein said electrically conductive material comprises a metal.
Claim 15
Dependent Claim
14 words
A method according to claim 11, wherein said electrically conductive material comprises a silicide.
Claim 16
Dependent Claim
30 words
A method according to claim 11, wherein said electrically conductive material contains a refractory metal for reducing the effective resistance of the electrically conductive material in said auxiliary trench region.
Claim 17
Dependent Claim
27 words
A method according to claim 11, wherein that portion of said electrically conductive material containing said refractory metal lies on a top surface portion of said polysilicon.
Claim 18
Dependent Claim
46 words
A method according to claim 9, wherein step (a) comprises forming said trench pattern and said auxiliary trench region in a semiconductor layer that is dielectrically isolated from an underlying substrate, so as to subdivide said semiconductor layer into a plurality of spaced-apart, dielectrically isolated islands.
Claim 19
Dependent Claim
20 words
A method according to claim 9, wherein step (a) comprises forming said auxiliary trench region in an electrically isolated island.
Claim 20
Dependent Claim
27 words
A method according to claim 17, further including forming at least one semiconductor device in the electrically isolated island in which said auxiliary trench region is formed.
Claim 21
Dependent Claim
25 words
A method according to claim 9, wherein step (a) comprises forming a plurality of auxiliary trench regions in said selected portion of said semiconductor layer.
Claim 22
Dependent Claim
22 words
A method according to claim 9, wherein step (a) comprises forming a plurality of auxiliary trench regions in an electrically isolated island.
Claim 23
Independent Claim
97 words
A method of manufacturing a semiconductor device comprising the steps of: (a) forming a plurality of trench regions in a semiconductor layer; (b) forming dielectric material on top surfaces of said semiconductor layer, and upon walls of said trench regions, so that said trench regions are electrically isolated from one another; (c) forming electrically conductive material in said trench regions; (d) coupling electrically conductive material in respective ones of said trench regions to respectively different portions of said semiconductor layer; and (e) coupling respectively different voltages to electrically conductive material in respective ones of said trench regions.
Claim 24
Independent Claim
97 words
A method of manufacturing a semiconductor device comprising the steps of: (a) forming a plurality of trench regions in a semiconductor layer; (b) forming dielectric material on top surfaces of said semiconductor layer, and upon walls of said trench regions, so that said trench regions are electrically isolated from one another; (c) forming electrically conductive material in said trench regions; (d) coupling electrically conductive material in respective ones of said trench regions to respectively different portions of said semiconductor layer; and (e) coupling respectively different voltages to electrically conductive material in respective ones of said trench regions.
References Cited (Backward Citations)
EP0143662A2
Cited
JPS62113422A
Cited
JPS63310133A
Cited
JPS6413744A
Cited
JPS6441219A
Cited
US4889832A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-03-22 | 1996-09-21 | 1997-03-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-03-22 | 2000-09-21 | 2001-03-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-03-22 | 2004-09-21 | 2005-03-23 | $7700.00 | Window Closed / Lapsed |