US5837562A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Process for bonding a shell to a substrate for packaging a semiconductor
Assignee: Charles Stark Draper Laboratory Inc
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Filing: 1995-07-07
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Granted: 1998-11-17
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Expires: 2015-07-07
Abstract
Abstract A process for manufacturing a vacuum enclosure for a semiconductor device formed on a substrate with leads extending peripherally. Assembly of the enclosure is compatible with known batch fabrication techniques and is carried out at pressures required for optimal device operation. In a first embodiment, an intrinsic silicon shell is sealed to the substrate via electrostatic or anodic bonding with the leads diffusing into the shell. In a second embodiment, a thin interface layer of silicon or polysilicon is deposited on the substrate prior to electrostatic bonding a glass shell thereon. In a third embodiment, tunnels are formed between a lower peripheral edge of the shell and the substrate, allowing leads to pass thereunder. The tunnels are sealed by a dielectric material applied over the enclosure.
Inventors
- 👤 Steve T. Cho
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 18:15
CPC Classifications
H; H10; H10W; H10W95/00; G; G01; G01P; G01P1/00; G01P1/02; G01P1/023; H10W76/00; H10W76/10; H10W76/12; H10W76/15; H10W76/157; H10W76/60
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
118 words
A method for forming a vacuum enclosure enclosing a semiconductor device, said method comprising: providing a substrate; disposing a semiconductor device on said substrate; forming a plurality of electrical leads in communication with said semiconductor device on said substrate, wherein said step of forming further comprises depositing a lower layer of refractory metal on said substrate, and depositing an upper layer of soft metal over said lower layer; positioning a shell having a concave surface with surrounding edges on said substrate, on said plurality of electrical leads, and over said semiconductor device; and anodically bonding said shell to said substrate, including eutectically sealing said shell edges to said upper layer of each of said plurality of electrical leads.
Claim 2
Independent Claim
118 words
A method for forming a vacuum enclosure enclosing a semiconductor device, said method comprising: providing a substrate; disposing a semiconductor device on said substrate; forming a plurality of electrical leads in communication with said semiconductor device on said substrate, wherein said step of forming further comprises depositing a lower layer of refractory metal on said substrate, and depositing an upper layer of soft metal over said lower layer; positioning a shell having a concave surface with surrounding edges on said substrate, on said plurality of electrical leads, and over said semiconductor device; and anodically bonding said shell to said substrate, including eutectically sealing said shell edges to said upper layer of each of said plurality of electrical leads.
Claim 3
Dependent Claim
18 words
The method according to claim 1, wherein said step of providing a substrate includes providing a glass substrate.
Claim 4
Dependent Claim
22 words
The method according to claim 1, wherein said step of disposing said semiconductor device includes fabricating said semiconductor device on said substrate.
Claim 5
Dependent Claim
20 words
The method according to claim 1, wherein said step of positioning said shell further comprises positioning a high-resistivity silicon shell.
Claim 6
Dependent Claim
25 words
The method according to claim 1, wherein said step of positioning said shell further comprises depositing a high-resistivity silicon layer on said shell lower edge.
Claim 7
Dependent Claim
24 words
The method according to claim 5, wherein said step of bonding further comprises eutectically sealing said silicon layer to said plurality of electrical leads.
Claim 8
Dependent Claim
35 words
The method according to claim 1, wherein said step of positioning said shell further comprises aligning a plurality of ports disposed in said shell edges with respective ones of said plurality of electrically conductive leads.
Claim 9
Dependent Claim
30 words
The method according to claim 7, wherein said step of bonding said shell further includes depositing a dielectric sealing material about said shell edges and within said plurality of ports.
Claim 10
Dependent Claim
24 words
The method according to claim 8, further including the step of etching said dielectric sealing material to expose electrically conductive pads proximate said shell.
Claim 11
Dependent Claim
59 words
The method according to claim 1, before the step of anodically bonding, further including: inserting spacers between said shell and said substrate; backfilling said enclosure with inert gas to evacuate moisture from within said enclosure; subjecting said enclosure to anodic bonding conditions to electrostatically outgas materials from said enclosure which could adversely effect subsequent bonding; and removing said spacers.
Claim 12
Independent Claim
114 words
A method for forming a vacuum enclosure enclosing a semiconductor device, said method comprising: providing a substrate; disposing a semiconductor device on said substrate; forming a plurality of electrical leads in communication with said semiconductor device on said substrate; positioning a shell having a concave surface with surrounding edges on said substrate, on said plurality of electrical leads, and over said semiconductor device; inserting spacers between said shell and said substrate; backfilling said enclosure with inert gas to evacuate moisture from within said enclosure; subjecting said enclosure to anodic bonding conditions to electrostatically outgas materials from said enclosure which could adversely effect subsequent bonding; removing said spacers; and bonding said shell to said substrate.
Claim 13
Independent Claim
114 words
A method for forming a vacuum enclosure enclosing a semiconductor device, said method comprising: providing a substrate; disposing a semiconductor device on said substrate; forming a plurality of electrical leads in communication with said semiconductor device on said substrate; positioning a shell having a concave surface with surrounding edges on said substrate, on said plurality of electrical leads, and over said semiconductor device; inserting spacers between said shell and said substrate; backfilling said enclosure with inert gas to evacuate moisture from within said enclosure; subjecting said enclosure to anodic bonding conditions to electrostatically outgas materials from said enclosure which could adversely effect subsequent bonding; removing said spacers; and bonding said shell to said substrate.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-11-16 | 2002-05-18 | 2002-11-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-11-16 | 2006-05-18 | 2006-11-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-11-16 | 2010-05-18 | 2010-11-17 | $7700.00 | Window Closed / Lapsed |