US5835401A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Dram with hidden refresh
Assignee: Rambus Inc
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Filing: 1996-12-05
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Granted: 1998-11-10
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Expires: 2016-12-05
Abstract
Abstract A method and circuit for hiding a refresh of DRAM cells in a memory device. One embodiment of the circuit includes a selection circuit configured to select a first row of DRAM cells in the memory circuit in response to an active control signal. As a result, data may be read from or written to at least one of the DRAM cells in the first row. The selection circuit is also configured to couple a refresh address to a second row of DRAM cells in the memory circuit in response to an inactive state control signal. The second row of cells is refreshed when the selection circuit accesses the second row. For one embodiment, the DRAM cells are four transistor DRAM cells.
Inventors
- 👤 Gary W. Green
- 👤 John Q. Torode
- 👤 T. J. Rodgers
- 👤 Shailesh Shah
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 04:56
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/406
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
108 words
A circuit comprising: a memory circuit having a first and second row of dynamic random access memory (DRAM) cells; and a multiplexer coupled to the memory circuit and receiving a select signal having a first state and a second state, wherein: the multiplexer couples a read/write address to the memory circuit when the select signal is in the first state, the read/write address selecting the first row of DRAM cells for writing or reading, and the multiplexer couples a refresh address to the memory circuit when the select signal is in the second state, the refresh address selecting the first or second row of DRAM cells for refreshing.
Claim 2
Dependent Claim
108 words
A circuit comprising: a memory circuit having a first and second row of dynamic random access memory (DRAM) cells; and a multiplexer coupled to the memory circuit and receiving a select signal having a first state and a second state, wherein: the multiplexer couples a read/write address to the memory circuit when the select signal is in the first state, the read/write address selecting the first row of DRAM cells for writing or reading, and the multiplexer couples a refresh address to the memory circuit when the select signal is in the second state, the refresh address selecting the first or second row of DRAM cells for refreshing.
Claim 3
Dependent Claim
47 words
The circuit of claim 1, wherein the circuit further comprises: a decoder configured to (i) receive the read/write address and the refresh address from the multiplexer and (ii) provide a decoded address to the memory circuit; and a refresh address generator configured to generate the refresh address.
Claim 4
Dependent Claim
38 words
The circuit of claim 1, wherein the circuit further comprises: a decoder configured to provide the read/write address to the multiplexer in response to a row address; and a refresh address generator configured to generate the refresh address.
Claim 5
Dependent Claim
20 words
The circuit of claim 1, wherein one of the DRAM cells in the second row comprises a four-transistor DRAM cell.
Claim 6
Dependent Claim
64 words
The circuit of claim 4, wherein: each DRAM cell in the second row is coupled to a wordline; and the four-transistor DRAM cell in the second row comprises: a first pair of transistors coupled to the wordline; and a second pair of transistors coupled to the first pair of transistors and cross coupled with each other, wherein the second pair of transistors store data.
Claim 7
Dependent Claim
21 words
The circuit of claim 1, comprising: a refresh address circuit coupled to the multiplexer and configured to generate the refresh address.
Claim 8
Dependent Claim
15 words
The circuit of claim 6, wherein the refresh address circuit comprises a shift register circuit.
Claim 9
Dependent Claim
15 words
The circuit of claim 6, wherein the refresh address circuit comprises an address counter circuit.
Claim 10
Dependent Claim
47 words
The circuit of claim 6, further comprising: a state monitor circuit coupled to the refresh address circuit and configured to monitor the refresh address, wherein if the refresh address is invalid, then the state monitor circuit causes the refresh address circuit to output a valid refresh address.
Claim 11
Dependent Claim
13 words
The circuit of claim 1, wherein the select signal comprises a clock signal.
Claim 12
Dependent Claim
14 words
The circuit of claim 1, wherein the select signal comprises a chip enable signal.
Claim 13
Dependent Claim
18 words
The circuit of claim 1, wherein the select signal comprises a chip enable signal and a clock signal.
Claim 14
Dependent Claim
66 words
The circuit of claim 10, further comprising: a clock adjusting circuit coupled to the refresh address circuit and the selection circuit, wherein the clock signal has a first frequency and the clock adjusting circuit generates an internal clock signal having a second frequency different than the first frequency, wherein the refresh address circuit is configured to generate the refresh address in response to the internal clock.
Claim 15
Dependent Claim
54 words
The circuit of claim 6, further comprising: a detector circuit coupled to the multiplexer, wherein the detector circuit monitors a frequency of the select signal and couples an internal control signal to the refresh address circuit in place of the select signal if the frequency of the select signal falls below a predetermined frequency.
Claim 16
Independent Claim
95 words
A method of operating a memory circuit having a first and second row of dynamic random access memory (DRAM) cells, comprising the steps of: providing a read/write address from a multiplexer to the memory circuit in response to a first state of a select signal, the read/write address selecting the first row of DRAM cells for writing or reading; and providing a refresh address from the multiplexer to the memory circuit in response to a second state of the select signal, the refresh address selecting the first or second row of DRAM cells for refreshing.
Claim 17
Independent Claim
95 words
A method of operating a memory circuit having a first and second row of dynamic random access memory (DRAM) cells, comprising the steps of: providing a read/write address from a multiplexer to the memory circuit in response to a first state of a select signal, the read/write address selecting the first row of DRAM cells for writing or reading; and providing a refresh address from the multiplexer to the memory circuit in response to a second state of the select signal, the refresh address selecting the first or second row of DRAM cells for refreshing.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-11-09 | 2002-05-11 | 2002-11-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-11-09 | 2006-05-11 | 2006-11-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-11-09 | 2010-05-11 | 2010-11-10 | $7700.00 | Window Closed / Lapsed |