Dual port type semiconductor memory

Claim 1

A semiconductor memory including a dynamic type random access memory (RAM) comprising a plurality of word lines (W₁... W n ); a plurality of pairs of bit lines (BL, BL ); a plurality of dynamic memory cells (MC') each cell being connected between respective word lines and bit lines at each intersection of the word lines and the pairs of bit lines respectively; a plurality of first column decoders (CD₁) each connected to a common writing-reading out bus (B₁), and to a respective pair of bit lines, wherein each of the first column decoders (CD₁) is connected to the writing-reading out bus (B₁) through a pair of gates (G₁) comprising two transistors connected to the respective bit lines to enable data to be transfered either from the bit lines to the writing-reading out bus (B₁) or from the writing-reading out bus (B₁) to the bit lines; and a plurality of sense amplifiers (SA) each connected to a respective pair of bit lines to store temporarily data in a selected memory cell to prevent destruction of the data during a reading operation; characterised in that the memory comprises a dual port memory, the memory further comprising a plurality of second column decoders (CD₂) each connected to a common reading out bus (B₂), and to a respective pair of bit lines, wherein each of the second column decoders (CD₂) is connected to the reading out bus (B₂) through a pair of gates (G₂) comprising four transistors, gate electrodes of two of the four transistors being connected to the bit lines and the other two of the four transistors being connected to the reading out bus (B₂) to enable data to be transferred only from the bit lines to the reading out bus (B₂).