Semiconductor memory device

Claim 2

A semiconductor memory device comprising a semiconductive substrate (30) having a surface and a first conductivity type, and a plurality of cell groups (10, 20,...) which are formed on said substrate (30) and each of which includes a predetermined number of memory cells (12, 14, 16, 18; 22, 24, 26, 28) each having a switching transistor (Q) and a capacitor (C), characterized in that said memory cells (12, 14, 16, 18; 22, 24, 26, 28) included in one cell group (10, 20) have a predetermined area (Al, A2) of a substantially rectangular shape upon the substrate surface being radially arranged in said predetermined area with respect to an intersection of diagonal lines of said predetermined area (Al, A2) as a center, and that said one cell group (10, 20) has a single semiconductor layer (120) of a second conductivity type in said predetermined area (Al, A2) so as to serve as a common drain region for all the transistors (Q) included therein.

Claim 3

The device as recited in claim 1, characterized in that said one cell group (10) includes four memory cells (12, 14, 16, 18) which are arranged along the diagonal lines of said predetermined area (Al) in a cross-shape, and four capacitors (Cl, C2, C3, C4) which are included in said four memory cells (12, 14, 16, 18) and are arranged inside four corners of said predetermined area (Al).

Claim 4

The device as recited in claim 1, characterized in that said one cell group (10) occupies a predetermined area (Al) of a substantially square shape of the substrate surface and includes first to fourth memory cells (12, 14, 16, 18) which respectively have first to fourth transistors ( Q l, Q2, Q3, Q4), said first to fourth transistors (Ql, Q2, Q3, Q4) being connected to each other through said semiconductor layer (120) as a common drain region formed at an intersection between first and second diagonal lines of said predetermined area (Al) and being arranged along the first and second - diagonal lines in a cross-shape, said first and second cells (12, 14) opposing each other and said third and fourth cells (16, 18) opposing each other.

Claim 5

The device as recited in claim 3, characterized in that said first to fourth cells (12, 14, 16, 18) respectively have first to fourth capacitors (Cl, C2, C3, C4) , said first and second capacitors (Cl, C2) being respectively connected directly to said first and second transistors (Ql, Q2) opposing each other along the first diagonal line and being arranged at first and second corners corresponding to the first diagonal line of said predetermined area (Al), and said third and fourth capacitors (C3, C4) being respectively connected directly to said third and fourth transistors (Q3, Q4) opposing each other along the second diagonal line and being arranged at third and fourth corners corresponding to the second diagonal line of said predetermined area (Al).

Claim 6

The device as recited in claim 4, characterized by further comprising a first conductive layer (110) which is provided above said substrate (30) so as to be electrically insulated therefrom and which serves as a common capacitor electrode for all the capacitors (C) of said memory device, said all the capacitors (C) including said first to fourth capacitors (Cl, C2, C3, C4) included in said one cell group (10); a second conductive layer (G 1 ) which is provided above said first conductive layer (110) so as to be electrically insulated therefrom and which includes first gate electrode lines (G12, G 11 ) respectively connected to gates of said first and second transistors (Ql, Q2); and a third conductive layer (G 2 ) which is provided above said second conductive layer (G 1 ) so as to be electrically insulated therefrom and which includes second gate electrode lines (G21, G 22 ) respectively connected to gates of said third and fourth transistors (Q3, Q4).

Claim 7

The device as recited in claim 5, characterized in that said first to third conductive layers (110, G 1 , G 2 ) comprise a polycrystalline silicon material.

Claim 8

The device as recited in claim 5, characterized by further comprising a fourth conductive layer (124) which is provided above said third conductive layer (G 2 ) so as to be insulated therefrom and which includes a drain electrode line (124) connected to said common drain region (120) of said first to fourth transistors (Ql, Q2, Q3, Q4).

Claim 9

A dynamic semiconductor memory device comprising a semiconductive substrate (30) having a surface, characterized by further comprising a first cell unit (10) which occupies a first area (Al) of a substantially square shape upon the substrate surface and which has four memory cells (12, 14, 16, 18) arranged along two diagonal lines of said first area (Al) in a cross-shape such that each of said four memory cells (12, 14, 16, 18) has a MOS switching transistor (Q) and a MOS capacitor (C), said first cell unit (10) having a diffusion layer (120) formed at substantially a center of said first area (Al) so as to serve as a common drain region for first to fourth transistors (Ql, Q2, Q3, Q4) comprising said MOS switching transistors included in said first cell unit (10), said first to fourth transistors (Ql, Q2, Q3, Q4) being arranged along said two diagonal lines in a cross-shape, and first to fourth capacitors (Cl, C2, C3, C4) comprising said MOS capacitors of said four memory cells being arranged inside corners of said first area (Al); a second cell unit (20) which occupies a second area (A2) of a substantially square shape upon the substrate surface and is adjacent to said first cell unit (10) and which has four memory cells (22, 24, 26, 28) arranged along two diagonal lines of said second area (A2) in a cross-shape, said second cell unit (20) having fifth to eighth transistors (Q5, Q6, Q7, Q8) comprising MOS switching transistors and fifth to eighth capacitors (C5, C6, C7, C8) comprising MOS capacitors which are arranged in the same manner as in said first cell unit (10); and a conductive layer (110) which comprises polycrystalline silicon corresponding to a common capacitor electrode for said first to eighth capacitors (Cl, C2, C3, C4, C5, C6, C7, C8) and which is formed above said substrate (30) so as to be insulated therefrom.

Claim 10

A dynamic semiconductor memory device comprising a semiconductive substrate (30) having a surface, characterized by further comprising a first cell unit (10) which occupies a first area (Al) of a substantially square shape upon the substrate surface and which has four memory cells (12, 14, 16, 18) arranged along two diagonal lines of said first area (Al) in a cross-shape such that each of said four memory cells (12, 14, 16, 18) has a MOS switching transistor (Q) and a MOS capacitor (C), said first cell unit (10) having a diffusion layer (120) formed at substantially a center of said first area (Al) so as to serve as a common drain region for first to fourth transistors (Ql, Q2, Q3, Q4) comprising said MOS switching transistors included in said first cell unit (10), said first to fourth transistors (Ql, Q2, Q3, Q4) being arranged along said two diagonal lines in a cross-shape, and first to fourth capacitors (Cl, C2, C3, C4) comprising said MOS capacitors of said four memory cells being arranged inside corners of said first area (Al); a second cell unit (20) which occupies a second area (A2) of a substantially square shape upon the substrate surface and is adjacent to said first cell unit (10) and which has four memory cells (22, 24, 26, 28) arranged along two diagonal lines of said second area (A2) in a cross-shape, said second cell unit (20) having fifth to eighth transistors (Q5, Q6, Q7, Q8) comprising MOS switching transistors and fifth to eighth capacitors (C5, C6, C7, C8) comprising MOS capacitors which are arranged in the same manner as in said first cell unit (10); and a conductive layer (110) which comprises polycrystalline silicon corresponding to a common capacitor electrode for said first to eighth capacitors (Cl, C2, C3, C4, C5, C6, C7, C8) and which is formed above said substrate (30) so as to be insulated therefrom.

Claim 11

The device as recited in claim 8, characterized in that said first and second transistors (Ql, Q2) included in said first cell unit (10) oppose each other along the first diagonal line between said two diagonal lines of said first area (Al), said first diagonal line corresponding to a first direction (Y) on the substrate surface, while said third and fourth transistors (Q3, Q4) oppose each other along the second diagonal line which corresponds to a second direction (X), and wherein said fifth and sixth transistors (Q5, Q6) included in said second cell unit (20) oppose each other along the first direction (Y), while said seventh and eighth transistors (Q7, Q8) oppose each other along the second direction (X).

Claim 12

The device as recited in claim 9, characterized by further comprising a second conductive layer (G 1 ) of polycrystalline silicon formed above said first conductive layer (110) so as to be insulated therefrom, and in that said second conductive layer includes a first gate electrode wiring line (G 11 ) which extends parallel to the first direction (Y) and which has a first branch line portion (G 11 ') extending therefrom along the second direction (X) and connected to a gate of said second transistor (Q2), a second gate electrode wiring line (G 12 ) which extends parallel to the first direction ( Y ) and which has a second branch line portion (G 12 ') extending therefrom along the second direction (X) and connected to a gate of said first. transistor (Ql), and a third gate electrode wiring line (G 13 ) which extends parallel to the first direction (Y) and connected to a gate of said eighth transistor (Q8).

Claim 13

The device as recited in claim 10, characterized by further comprising a third conductive layer (G 2 ) of polycrystalline silicon formed above said second conductive layer (G l ) so as to be electrically insulated therefrom, and in that said third conductive layer (G 2 ) includes a fourth gate electrode wiring line (G 21 ) which extends parallel to the first direction (Y) and connected to a gate of said third transistor (Q3), a fifth gate electrode wiring line (G 22 ) which extends parallel to the first direction (Y) and which has a third branch line portion (G 22 1 ) extending therefrom along the second direction (X) and connected to a gate of said sixth transistor (Q6), and a sixth gate electrode wiring line (G 23 ) which extends parallel to the first direction (Y) and which has a fourth branch line portion (G 23 ') extending therefrom along the second direction (X) and connected to a gate of said fifth transistor (Q5).