Patent US5834849A successfully refreshed from Google Patents.
US5834849A
Expired / Lapsed
US
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High density integrated circuit pad structures
Assignee: Altera Corp
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Filing: 1996-02-13
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Granted: 1998-11-10
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Expires: 2016-02-13
Abstract
Abstract An integrated circuit with high density pad structures is provided. The circuit has circuitry covered by an insulating layer. Pads are formed on the insulating layer overlapping the circuitry. A pattern of holes in the insulating layer allows electrical connections to be formed between the pads and the underlying circuitry. Because the pads are formed on top of the circuitry, the die area occupied by pads is reduced relative to the die area occupied by circuitry. The pads are suitable for flip-chip bonding to a package such as a multichip module or conventional wire bonding.
Inventors
- 👤 Christopher F. Lane
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 08:59
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
87 words
An integrated circuit, comprising: a die having an upper surface; circuitry formed on the upper surface of said die; an insulating layer disposed on said circuitry and having a plurality of holes; and a plurality of pads on said insulating layer overlapping said circuitry and electrically connected to said circuitry through said holes, wherein said pads are arranged in an inner row and an outer row, said inner row of pads further comprising extended portions for connecting to said circuitry through said holes in said insulating layer.
Claim 2
Dependent Claim
87 words
An integrated circuit, comprising: a die having an upper surface; circuitry formed on the upper surface of said die; an insulating layer disposed on said circuitry and having a plurality of holes; and a plurality of pads on said insulating layer overlapping said circuitry and electrically connected to said circuitry through said holes, wherein said pads are arranged in an inner row and an outer row, said inner row of pads further comprising extended portions for connecting to said circuitry through said holes in said insulating layer.
Claim 3
Dependent Claim
21 words
The integrated circuit defined in claim 1 wherein said extended portions extend radially outward between said pads in said outer row.
Claim 4
Dependent Claim
40 words
The integrated circuit defined in claim 1 wherein each of said holes through which said extended portions of said inner row of pads connect to said circuitry is disposed between a respective pair of said pads in said outer row.
Claim 5
Dependent Claim
20 words
The integrated circuit defined in claim 1 wherein said pads are solder ball pads for flip-chip mounting said integrated circuit.
Claim 6
Dependent Claim
13 words
The integrated circuit defined in claim 1 wherein said pads are bonding pads.
Claim 7
Dependent Claim
82 words
An integrated circuit, comprising: a die having an upper surface; circuitry formed on the upper surface of said die; an insulating layer disposed on said circuitry and having a plurality of holes; and a plurality of pads on said insulating layer overlapping said circuitry and electrically connected to said circuitry through said holes, wherein said pads are disposed in a two-dimensional array of intersecting rows and columns of said pads, said array having more than two rows and more than two columns.
Claim 8
Dependent Claim
82 words
An integrated circuit, comprising: a die having an upper surface; circuitry formed on the upper surface of said die; an insulating layer disposed on said circuitry and having a plurality of holes; and a plurality of pads on said insulating layer overlapping said circuitry and electrically connected to said circuitry through said holes, wherein said pads are disposed in a two-dimensional array of intersecting rows and columns of said pads, said array having more than two rows and more than two columns.
Claim 9
Dependent Claim
20 words
The integrated circuit defined in claim 6 wherein said pads are solder ball pads for flip-chip mounting said integrated circuit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-11-09 | 2002-05-11 | 2002-11-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-11-09 | 2006-05-11 | 2006-11-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-11-09 | 2010-05-11 | 2010-11-10 | $7700.00 | Window Closed / Lapsed |