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JPH03280441A Expired / Lapsed JP ⏱️ 0.0 years remaining

Semiconductor device

Assignee: Toshiba Corp
•
Filing: 1990-03-29
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Granted: —
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Expires: 2010-03-29
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Abstract

Abstract PURPOSE:To enlarge the area of a memory cell part and the areas of bonding pads and to improve the connection strength of the bonding pads by a method wherein the bonding pads are formed on an device. CONSTITUTION:An insulating film 3 consisting of SiO2 or the like is formed on a gate electrode 2 constituting a MOSFET of a semiconductor chip 1, on which a multitude of elements are integrated and formed. Electrodes 6, to which bonding pads are connected, are formed on the film 3 on the periphery of the chip simultaneously with the formation of Al wirings 5, which are respectively connected to diffused layers 4 of the FET, on the film 3. A second layer insulating film 7 consisting of SiO2 or the like is formed and contact holes 8 are formed in the part only of the electrode 6 by photoetching. The bonding pads 9 are formed by a sputtering method. As the surfaces of the bonding pads are provided within a memory cell region, the areas of the bonding pads can be excluded from the area of the chip. Thereby, the miniaturization of a wiring pattern can be prevented by enlarging the area of the memory cell part and the sufficient bonding connection strength of the bonding pads is obtained.

Inventors

  • 👤 Mitsuhiro Aono
  • 👤 光弘 青野
  • 👤 Yuji Inoue
  • 👤 井上 祐治

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-09 09:02
CPC Classifications
H; H10; H10W; H10W72/00; H10W72/90; H10W70/00; H10W70/60; H10W72/071; H10W72/075; H10W72/07551; H10W72/50; H10W72/531; H10W72/5363; H10W72/59; H10W72/921; H10W72/923; H10W72/931; H10W72/932; H10W72/934; H10W72/951; H10W72/952

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