Interconnect scheme for integrated circuits

Claim 2

A multilayer interconnect structure for connecting conductive regions to conductive regions separated by insulating regions supported on a semiconductor substrate, said semiconductor substrate containing conducting regions therein which are electrically contacted by portions of said multilayer interconnect structure, said multilayer interconnect structure further comprising a plurality of planar structures stacked one on top of another over said semiconductor substrate, each planar structure having a top surface and a bottom surface and having at least one adjacent planar structure contacting said top surface, said bottom surface, or both, and each planar structure comprising a patterned metal layer comprising either a single conductor layer or said conductor layer and a substantially thinner barrier layer, said single conductor layer comprising metal selected from the group consisting of aluminum, aluminum alloy, tungsten, and copper, said single conductor layer in some of said plurality of planar structures comprising tungsten and said single conductor layer in others of said plurality of planar structures comprising aluminum, said patterned metal layer having a thickness, said patterned metal layer embedded in a dielectric, thereby forming metal regions and dielectric regions, said patterned metal layer exposed at both said top surface and said bottom surface of said planar structures, thereby enabling electrical contact to be formed between selected metal regions in said adjacent planar structures so as to form electrical connections along paths perpendicular to said semiconductor substrate and electrical connection on paths parallel to said semiconductor substrate, wherein each said planar structure simultaneously forms electrical connection along paths perpendicular to said semiconductor substrate and electrical connections along paths parallel to said semiconductor substrate and wherein said thickness across each of said patterned metal layers in each of said planar structures is essentially the same.

Claim 3

The multilayer interconnect structure of claim 1 wherein said plurality of planar structures are formed on an initial patterned metal layer contacting at least one of said conducting regions in said semiconductor substrate, said initial patterned metal layer embedded in said insulating regions plus an initial layer of said dielectric, at least one of said metal regions in said plurality of planar structures forming electrical contact with said initial patterned metal layer.

Claim 4

The multilayer interconnect structure of claim 1 wherein said substantially thinner barrier layer comprises a refractory metal.

Claim 5

The multilayer interconnect structure of claim 1 wherein the cross-section of each of said metal regions has a ratio of height to width not greater than 2.

Claim 6

The multilayer interconnect structure of claim 1 wherein said dielectric is selected from the group consisting of oxides, nitrides, and oxy-nitrides.

Claim 7

The multilayer interconnect structure of claim 5 wherein said dielectric is selected from the group consisting of silicon oxide, silicon nitride, silicon oxy-nitride, aluminum oxide, and boron nitride.

Claim 8

The multilayer interconnect structure of claim 1 further comprising an etch stop layer beneath at least one of said layers of said dielectric.

Claim 9

A multilayer interconnect structure for connecting conductive regions to conductive regions separated by insulating regions supported on a semiconductor substrate, said semiconductor substrate containing conducting regions therein which are electrically contacted by portions of said multilayer interconnect structure, said multilayer interconnect structure further comprising a plurality of planar structures stacked one on top of another over said semiconductor substrate, each planar structure having a top surface and a bottom surface and having at least one adjacent planar structure contacting said top surface, said bottom surface, or both, and each planar structure comprising a patterned metal layer comprising either a single conductor layer or said conductor layer and a substantially thinner barrier layer, said single conductor layer comprising metal selected from the group consisting of aluminum, aluminum alloy, tungsten, and copper, said single conductor layer in some of said plurality of planar structures comprising tungsten and said single conductor layer in others of said plurality of planar structures comprising aluminum, said patterned metal layer having a thickness, said patterned metal layer embedded in a dielectric, thereby forming metal regions and dielectric regions, said dielectric layer formed on top of an etch stop layer, said patterned metal layer exposed at both said top surface and said bottom surface of said planar structures, thereby enabling electrical contact to be formed between selected metal regions in said adjacent planar structures so as to form electrical connections along paths perpendicular to said semiconductor substrate and electrical connection on paths parallel to said semiconductor substrate, wherein each said planar structure simultaneously forms electrical connection along paths perpendicular to said semiconductor substrate and electrical connections along paths parallel to said semiconductor substrate and wherein said thickness across each of said patterned metal layers in each of said planar structures is essentially the same.

Claim 10

A multilayer interconnect structure for connecting conductive regions to conductive regions separated by insulating regions supported on a semiconductor substrate, said semiconductor substrate containing conducting regions therein which are electrically contacted by portions of said multilayer interconnect structure, said multilayer interconnect structure further comprising a plurality of planar structures stacked one on top of another over said semiconductor substrate, each planar structure having a top surface and a bottom surface and having at least one adjacent planar structure contacting said top surface, said bottom surface, or both, and each planar structure comprising a patterned metal layer comprising either a single conductor layer or said conductor layer and a substantially thinner barrier layer, said single conductor layer comprising metal selected from the group consisting of aluminum, aluminum alloy, tungsten, and copper, said single conductor layer in some of said plurality of planar structures comprising tungsten and said single conductor layer in others of said plurality of planar structures comprising aluminum, said patterned metal layer having a thickness, said patterned metal layer embedded in a dielectric, thereby forming metal regions and dielectric regions, said dielectric layer formed on top of an etch stop layer, said patterned metal layer exposed at both said top surface and said bottom surface of said planar structures, thereby enabling electrical contact to be formed between selected metal regions in said adjacent planar structures so as to form electrical connections along paths perpendicular to said semiconductor substrate and electrical connection on paths parallel to said semiconductor substrate, wherein each said planar structure simultaneously forms electrical connection along paths perpendicular to said semiconductor substrate and electrical connections along paths parallel to said semiconductor substrate and wherein said thickness across each of said patterned metal layers in each of said planar structures is essentially the same.

Claim 11

The multilayer interconnect structure of claim 8 wherein said plurality of planar structures are formed on an initial patterned metal layer contacting at least one of said conducting regions in said semiconductor substrate, said initial patterned metal layer embedded in said insulating regions plus an initial layer of said dielectric, at least one of said metal regions in said plurality of planar structures forming electrical contact with said initial patterned metal layer.

Claim 12

The multilayer interconnect structure of claim 8 wherein said substantially thinner barrier layer comprises a refractory metal.

Claim 13

The multilayer interconnect structure of claim 8 wherein each said planar structures simultaneously forms electrical connection along paths perpendicular to said semiconductor substrate and electrical connection along paths parallel to said semiconductor substrate.

Claim 14

The multilayer interconnect structure of claim 8 wherein the cross-section of each of said metal regions has a ratio of height to width not greater than about 2.

Claim 15

The multilayer interconnect structure of claim 8 wherein said dielectric is selected from the group consisting of oxides, nitrides, and oxy-nitrides.

Claim 16

The multilayer interconnect structure of claim 13 wherein said dielectric is selected from the group consisting of silicon oxide, silicon nitride, silicon oxy-nitride, aluminum oxide, and boron nitride.

Claim 17

A multilayer interconnect structure for connecting conductive regions to conductive regions separated by insulating regions supported on a semiconductor substrate, said semiconductor substrate containing conducting regions therein which are electrically contacted by portions of said multilayer interconnect structure, said multilayer interconnect structure comprising a plurality of planar structures stacked one on top of another over said semiconductor substrate, each planar structure having a top surface and a bottom surface and having at least one adjacent planar structure contacting said top surface, said bottom surface, or both, and each planar structure comprising a patterned metal layer comprising either a single conductor layer or said single conductor layer and a substantially thinner barrier layer, said patterned metal layer embedded in a dielectric, thereby forming metal regions and dielectric regions, said patterned metal layer exposed at both said top surface and said bottom surface of said planar structures, thereby enabling electrical contact to be formed between selected metal regions in said adjacent planar structures so as to form electrical connection along paths perpendicular to said semiconductor substrate and electrical connection on paths parallel to said semiconductor substrate, wherein some of said single conductor layers comprise tungsten and other of said single conductor layers comprise aluminum.

Claim 18

A multilayer interconnect structure for connecting conductive regions to conductive regions separated by insulating regions supported on a semiconductor substrate, said semiconductor substrate containing conducting regions therein which are electrically contacted by portions of said multilayer interconnect structure, said multilayer interconnect structure comprising a plurality of planar structures stacked one on top of another over said semiconductor substrate, each planar structure having a top surface and a bottom surface and having at least one adjacent planar structure contacting said top surface, said bottom surface, or both, and each planar structure comprising a patterned metal layer comprising either a single conductor layer or said single conductor layer and a substantially thinner barrier layer, said patterned metal layer embedded in a dielectric, thereby forming metal regions and dielectric regions, said patterned metal layer exposed at both said top surface and said bottom surface of said planar structures, thereby enabling electrical contact to be formed between selected metal regions in said adjacent planar structures so as to form electrical connection along paths perpendicular to said semiconductor substrate and electrical connection on paths parallel to said semiconductor substrate, wherein some of said single conductor layers comprise tungsten and other of said single conductor layers comprise aluminum.

Claim 19

The multilayer interconnect structure of claim 15 wherein said plurality of planar structures are formed on an initial patterned metal layer contacting at least one of said conducting regions in said semiconductor substrate, said initial patterned metal layer embedded in said insulating regions plus an initial layer of said dielectric, at least one of said metal regions in said plurality of planar structures forming electrical contact with said initial patterned metal layer.

Claim 20

The multilayer interconnect structure of claim 15 wherein said substantially thinner barrier layer comprises a refractory metal.

Claim 21

The multilayer interconnect structure of claim 15 wherein each said planar structure simultaneously forms electrical connection along paths perpendicular to said semiconductor substrate and electrical connection along paths parallel to said semiconductor substrate.

Claim 22

The multilayer interconnect structure of claim 15 wherein the cross-section of each of said metal regions has a ratio of height to width not greater than 2.

Claim 23

The multilayer interconnect structure of claim 15 wherein the thickness of each of said patterned metal layers in each of said planar structures is essentially the same.

Claim 24

The multilayer interconnect structure of claim 15 wherein said single conductor layer comprises metal selected from the group consisting essentially of aluminum, aluminum alloy, tungsten, and copper.

Claim 25

The multilayer interconnect structure of claim 15 wherein said dielectric is selected from the group consisting of oxides, nitrides, and oxy-nitrides.

Claim 26

The multilayer interconnect structure of claim 22 wherein said dielectric is selected from the group consisting of silicon oxide, silicon nitride, silicon oxy-nitride, aluminum oxide, and boron nitride.

Claim 27

The multilayer interconnect structure of claim 15 further comprising an etch stop layer beneath at least one of said layers of said dielectric.

Claim 28

A multilayer interconnect structure for connecting conductive regions to conductive regions separated by insulating regions supported on a semiconductor substrate, said semiconductor substrate containing conducting regions therein that are electrically contacted by portions of said multilayer interconnect structure, said multilayer interconnect structure comprising a plurality of planar structures stacked one on top of another over said semiconductor substrate, each planar structure having a top surface and a bottom surface and having at least one adjacent planar structure contacting said top surface, said bottom surface, or both, and each planar structure comprising a patterned metal layer comprising either a single conductor layer or said single conductor layer and a substantially thinner barrier layer, said patterned metal layer embedded in a dielectric, thereby forming metal regions and dill electric regions, said dielectric formed on top of an etch stop layer, said patterned metal layer exposed at both said top surface and said bottom surface of said planar structures, thereby enabling electrical contact to be formed between selected metal regions in said adjacent planar structures so as to form electrical connection along paths perpendicular to said semiconductor substrate and electrical connection on paths parallel to said semiconductor substrate, wherein some of said single conductor layers comprise tungsten and other of said single conductor layers comprise aluminum.

Claim 29

A multilayer interconnect structure for connecting conductive regions to conductive regions separated by insulating regions supported on a semiconductor substrate, said semiconductor substrate containing conducting regions therein that are electrically contacted by portions of said multilayer interconnect structure, said multilayer interconnect structure comprising a plurality of planar structures stacked one on top of another over said semiconductor substrate, each planar structure having a top surface and a bottom surface and having at least one adjacent planar structure contacting said top surface, said bottom surface, or both, and each planar structure comprising a patterned metal layer comprising either a single conductor layer or said single conductor layer and a substantially thinner barrier layer, said patterned metal layer embedded in a dielectric, thereby forming metal regions and dill electric regions, said dielectric formed on top of an etch stop layer, said patterned metal layer exposed at both said top surface and said bottom surface of said planar structures, thereby enabling electrical contact to be formed between selected metal regions in said adjacent planar structures so as to form electrical connection along paths perpendicular to said semiconductor substrate and electrical connection on paths parallel to said semiconductor substrate, wherein some of said single conductor layers comprise tungsten and other of said single conductor layers comprise aluminum.

Claim 30

The multilayer interconnect structure of claim 25 wherein said plurality of planar structures are formed on an initial patterned metal layer contacting at least one of said conducting regions in said semiconductor substrate, said initial patterned metal layer embedded in said insulating regions plus an initial layer of said dielectric, at least one of said metal regions in said plurality of planar structures forming electrical contact with said initial patterned metal layer.

Claim 31

The multilayer interconnect structure of claim 25 wherein said substantially thinner barrier layer comprises a refractory metal.

Claim 32

The multilayer interconnect structure of claim 25 wherein each of said planar structures simultaneously forms electrical connection along paths perpendicular to said semiconductor substrate and electrical connection along paths parallel to said semiconductor substrate.

Claim 33

The multilayer interconnect structure of claim 25 wherein the cross-section of each of said metal regions has a ratio of height to width not greater than 2.

Claim 34

The multilayer interconnect structure of claim 25 wherein the thickness of each of said patterned metal layers in each of said planar structures is essentially the same.

Claim 35

The multilayer interconnect structure of claim 25 wherein said single conductor layer comprises metal selected from the group consisting essentially of aluminum, aluminum alloy, tungsten, and copper.

Claim 36

The multilayer interconnect structure of claim 25 wherein said dielectric is selected from the group consisting of oxides, nitrides, and oxy-nitrides.

Claim 37

The multilayer interconnect structure of claim 32 wherein said dielectric is selected from the group consisting of silicon oxide, silicon nitride, silicon oxy-nitride, aluminum oxide, and boron nitride.