A process for forming vias on integrated circuits

Claim 2

A process for forming vias in an integrated circuit, said process characterized by comprising the steps of: (a) forming a layer of a first metal (14) on a semiconductor substrate (12); (b) forming a layer of a second metal (16) on said first metal layer; (c) etching said second metal layer (16) in a predetermined via pattern with a second etchant which reacts with said second metal and which is substantially unreactive with said first metal; and (d) forming said vias in predetermined spacial relationship with a predetermined interconnect pattern by etching said first metal layer (14), in said predetermined interconnect pattern, with a first etchant which reacts with said first metal and which is substantially unreactive with said second metal or with said semiconductor substrate.

Claim 3

The process in accordance with Claim 1. characterized in that said first metal comprises tungsten, said first etchant comprises a flourine based dry etchant, said second metal comprises aluminum and said second etchant comprises a chlorine base dry etchant.

Claim 4

The process in accordance with Claim 1, characterized in that said first metal comprises aluminum, said first etchant comprises a chlorine based dry etchant, said second metal comprises tungsten and said second etchant comprises a flourine based dry etchant.

Claim 5

The process in accordance with Claim 1, characterized by additionally comprising the steps of: (e) forming a first dielectric layer (22) on said semiconductor substrate over said interconnects (20) and said vias (18); and (f) forming a substantially planar surface on said first dielectric layer, which surface is substantially co-planar with the upper surfaces of said vias, by etching back said dielectric layer (22) using an etchant which reacts with said dielectric material at an etch rate which is greater than the etch rate at which said etchant reacts with said second metal.

Claim 6

The process in accordance with Claim 4, characterized in that said first dielectric layer comprises silicon dioxide and said etchant comprises a flourine based etchant.

Claim 7

The process in accordance with Claim 4, characterized in that steps (a) through (f) are repeated at least once to form at least a second set of vias and at least a second predetermined interconnect pattern.

Claim 8

The process in accordance with any one of Claims 4 to 6, characterized by additionally comprising the steps of: (g) forming a third layer of said first metal (26) on said planar surface; (h) etching said third layer in a second predetermined interconnect pattern; and (i) forming a layer of dielectric material over said second predetermined interconnect pattern and said first dielectric layer.

Claim 9

A process for fabricating a multi-level integrated circuit, said process characterized by comprising the steps of: (a) forming a first layer of metal on a semiconductor substrate (52): (b) forming a first level of interconnects (54) in said first metal layer in a first predetermined pattern; (c) forming a layer of a first dielectric material (56) on said semiconductor substrate over said first level of interconnects; (d) forming a substantially planar surface (58) on said first dielectric layer, which surface is substantially co-planar with the upper surfaces of said first level of interconnects (54), by etching back said dielectric layer (56) using an etchant which reacts with said dielectric material and not with the interconnect material; (e) forming a layer of a second dielectric material (60) on said surface of said first dielectric material (56) over the upper surfaces of said first level interconnects; (f) etching a predetermined pattern of via apertures (66) in said second dielectric layer (60), using an etchant which reacts with said second dielectric material and which is substantially unreactive with said first dielectric material and said first level interconnect material; (g) forming a second layer of metal (68) over said second dielectric material (60), which layer of metal extends into said via apertures (66) and contacts the upper surfaces of said first level interconnects; and (h) forming a second level of interconnects in said second metal layer in a second predetermined interconnect pattern having predetermined contacting relationship with said first level of interconnects through said via apertures.

Claim 10

A process for fabricating a multi-level integrated circuit, said process characterized by comprising the steps of: (a) forming a first layer of metal on a semiconductor substrate (52): (b) forming a first level of interconnects (54) in said first metal layer in a first predetermined pattern; (c) forming a layer of a first dielectric material (56) on said semiconductor substrate over said first level of interconnects; (d) forming a substantially planar surface (58) on said first dielectric layer, which surface is substantially co-planar with the upper surfaces of said first level of interconnects (54), by etching back said dielectric layer (56) using an etchant which reacts with said dielectric material and not with the interconnect material; (e) forming a layer of a second dielectric material (60) on said surface of said first dielectric material (56) over the upper surfaces of said first level interconnects; (f) etching a predetermined pattern of via apertures (66) in said second dielectric layer (60), using an etchant which reacts with said second dielectric material and which is substantially unreactive with said first dielectric material and said first level interconnect material; (g) forming a second layer of metal (68) over said second dielectric material (60), which layer of metal extends into said via apertures (66) and contacts the upper surfaces of said first level interconnects; and (h) forming a second level of interconnects in said second metal layer in a second predetermined interconnect pattern having predetermined contacting relationship with said first level of interconnects through said via apertures.

Claim 11

The process in accordance with Claim 8, characterized by additionally comprising the step of forming a layer of dielectric material over said second predetermined interconnect pattern and said second dielectric material.

Claim 12

The process in accordance with Claim 8 characterized in that steps (c) through (h) are repeated at least once to form at least a third level of interconnects in predetermined contacting relationship with said second level of interconnects and additionally comprising the step of forming a top layer of dielectric material over said final level of interconnects.