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US4816895A Expired / Lapsed US ⏱️ 0.0 years remaining

Integrated circuit device with an improved interconnection line

Assignee: NEC Electronics Corp
•
Filing: 1987-03-05
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Granted: 1989-03-28
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Expires: 2007-03-05
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Abstract

Abstract A semiconductor device including interconnection lines for connecting element regions is disclosed. Each of interconnection lines is comprised of a first layer consisting essentially of aluminum, an alumina film formed on the first layer and a second layer containing silicon and deposited on the alumina film. Refractory metal silicide such as tungsten silicide, molybdenum silicide, titanium silicide, tantalum silicide and chrominum silicide is favorably employed as the second layer. Hillock formation and electromigration are thus prevented or suppressed.

Inventors

  • 👤 Takamaro Kikkawa

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-03 11:14
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/41; H10W20/44; H10W20/4451; H10W20/425

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 159 words
A semiconductor device comprising a semiconductor substrate, at least one element region formed in said semiconductor substrate, an insulating film covering said semiconductor substrate and having a contact hole which exposes one portion of said at least one element region, a first interconnection line making contact with said one portion of said at least one element region through said contact hole and extending over said insulating film, and a second interconnection line formed on said insulating film separately from said first interconnection line, each of said first and second interconnection lines comprising an aluminum layer, an alumina film formed on said aluminum layer, and a refractory metal silicide layer formed on said alumina film, said alumina film preventing an alloy reaction between said aluminum layer and said refractory metal silicide layer, said refractory metal silicide layer inhibiting hillock formation of said aluminum layer and electromigration of aluminum in said aluminum layer to prevent a breakdown of said interconnection lines.
Claim 2
Dependent Claim 159 words
A semiconductor device comprising a semiconductor substrate, at least one element region formed in said semiconductor substrate, an insulating film covering said semiconductor substrate and having a contact hole which exposes one portion of said at least one element region, a first interconnection line making contact with said one portion of said at least one element region through said contact hole and extending over said insulating film, and a second interconnection line formed on said insulating film separately from said first interconnection line, each of said first and second interconnection lines comprising an aluminum layer, an alumina film formed on said aluminum layer, and a refractory metal silicide layer formed on said alumina film, said alumina film preventing an alloy reaction between said aluminum layer and said refractory metal silicide layer, said refractory metal silicide layer inhibiting hillock formation of said aluminum layer and electromigration of aluminum in said aluminum layer to prevent a breakdown of said interconnection lines.
Claim 3
Dependent Claim 27 words
The device as claimed in claim 1, wherein said refractory metal silicide layer is selected from tungsten silicide, molybdenum silicide, titanium silicide, tantalum silicide and chromium silicide.
Claim 4
Dependent Claim 23 words
The device as claimed in claim 1, wherein said aluminum layer contains a metal selected from the group consisting of silicon and copper.
Claim 5
Dependent Claim 17 words
The device as claimed in claim 1, wherein said alumina film has a thickness of about 50Å.

References Cited (Backward Citations)

US3699011A Cited
US3702427A Cited
US4003772A Cited
US4180596A Cited
US4190466A Cited
US4561009A Cited
US4566940A Cited
US4554572A Cited
US4507852A Cited
US4734754A Cited
GB2169446A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1992-03-27 1992-09-26 1993-03-28 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1996-03-27 1996-09-26 1997-03-28 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2000-03-27 2000-09-26 2001-03-28 $7700.00 Window Closed / Lapsed

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