Microprocessor arranged for synchronously accessing an external memory with a scalable clocking mechanism

Claim 2

A computing system for accessing an external memory operating at a lower clock rate than a microprocessor, the computing system comprising: a clock circuit producing clock pulses at an external memory accessing rate and at a processing clock rate, an external memory coupled to the clock circuit, operating at the external memory accessing rate associated with the lower clock rate; and an integrated microprocessor coupled to the external memory and the clock circuit, operating at the processing clock rate, the integrated microprocessor being coupled to the external memory for synchronously and directly loading data from and storing data in the external memory, whereby the integrated microprocessor continues to operate at the processing clock rate while the external memory is accessed at the memory accessing rate.

Claim 3

The computing system of claim 1 wherein said external memory is coupled to a memory clock portion of said clock circuit for generating memory clock pulses at a first frequency for controlling said external memory accessing rate.

Claim 4

The computing system of claim 2 wherein said microprocessor is coupled to a processor clock portion of said clock circuit for generating processor clock pulses at a second frequency for controlling said processing clock rate.

Claim 5

The computing system of claim 1 wherein said microprocessor can operate either in a first mode wherein said external memory accessing rate is in a first relationship to said processing clock rate and wherein said microprocessor can operate in a second mode wherein said external memory accessing rate is in a second relationship to said processing clock rate.

Claim 6

The computing system of claim 4 wherein said microprocessor includes rate control inputs for controlling whether said microprocessor operates in said first mode or operates in said second mode.

Claim 7

The computing system of claim 5 wherein said processing clock rate is twice as high as said external memory accessing means when said microprocessor is operating in said second mode.

Claim 8

The computing system of claim 5 wherein said processing clock rate is three times as high as said external memory accessing means when said microprocessor is operating in said second mode.

Claim 9

The computing system of claim 1 wherein said processing clock rate is greater than the accessing rate of the external memory by at least 50 percent.

Claim 10

The computing system of claim 8 wherein said processing clock rate is an integer multiple of said external memory accessing rate.

Claim 11

The computing system of claim 9 wherein said processing clock rate is twice as high as said external memory accessing rate.

Claim 12

The computing system of claim 9 wherein said processing clock rate is three times higher than said external memory accessing rate.

Claim 13

The computing system of claim 9 wherein said processing clock rate is four times higher than said external memory accessing rate.

Claim 14

An integrated microprocessor arranged to access an external memory for executing load and store operations in synchronism with a memory clock which provides memory clock pulses at a first frequency for controlling the accessing rate of the external memory, said microprocessor comprising: an internal clock circuit, the internal clock circuit generating clock pulses at a second frequency for controlling a processing rate of said microprocessor, the second frequency being greater than the first frequency; a central processing unit coupled to the internal clock circuit and operating at the processing rate in response to the clock pulses at the second frequency; and a memory access controller coupled to the memory and receiving the memory clock pulses, the memory access controller directly accessing the memory in synchronism with the memory clock pulses while the central processing unit is operating at the processing rate.

Claim 15

An integrated microprocessor arranged to access an external memory for executing load and store operations in synchronism with a memory clock which provides memory clock pulses at a first frequency for controlling the accessing rate of the external memory, said microprocessor comprising: an internal clock circuit, the internal clock circuit generating clock pulses at a second frequency for controlling a processing rate of said microprocessor, the second frequency being greater than the first frequency; a central processing unit coupled to the internal clock circuit and operating at the processing rate in response to the clock pulses at the second frequency; and a memory access controller coupled to the memory and receiving the memory clock pulses, the memory access controller directly accessing the memory in synchronism with the memory clock pulses while the central processing unit is operating at the processing rate.

Claim 16

The integrated microprocessor as defined in claim 13 wherein the microprocessor includes an input for receiving the memory clock pulses from an external source.

Claim 17

The integrated microprocessor as defined in claim 13 wherein the microprocessor includes a clock generator for providing the memory clock pulses and an output for providing the memory clock pulses to the memory.

Claim 18

The integrated microprocessor as defined in claim 13 wherein a rate control signal indicates that the first frequency is related to the second frequency by a predetermined multiple of two.

Claim 19

The integrated microprocessor as defined in claim 16 wherein the rate control signal is a logical level one or a logical level zero.

Claim 20

The integrated microprocessor as defined in claim 16 wherein the memory clock pulses include a first phase portion and a second phase portion, wherein the memory is arranged to receive inputs from the microprocessor during the first phase portion and to provide outputs to the microprocessor during the second phase portion, and wherein the memory access controller includes enable means for enabling the microprocessor to provide outputs to the memory during the first phase portion and for enabling the microprocessor to receive inputs from the memory during said second phase portion.

Claim 21

The integrated microprocessor as defined in claim 18 wherein the internal clock circuit is arranged for generating first and second processor clock pulses, the first and second processor clock pulses being at the second frequency, having first and second clock pulse phases, and being of opposite phase relation, wherein the enable means is responsive to the rate control signal for enabling the microprocessor to provide the outputs to the memory upon the coincidence of each the first clock pulse first phase and the memory clock pulse first phase portion and to receive inputs from the external memory upon the coincidence of each the second clock pulse first phase and the memory clock pulse second phase portion.

Claim 22

The integrated microprocessor as defined in claim 19 wherein the enable means is further responsive to said rate control signal for enabling the microprocessor to provide said outputs to said external memory upon the coincidence of every other the first clock pulse first phase and the memory clock pulse first phase portion and to receive inputs from the memory upon the coincidence of every other the second clock pulse first phase and the memory clock pulse second phase portion.

Claim 23

The integrated microprocessor as defined in claim 20 wherein the enable means includes means for generating a first control signal for enabling said microprocessor to provide said outputs to said external memory and a second control signal for enabling said microprocessor to receive said inputs from said external memory.

Claim 24

The integrated microprocessor as defined in claim 18 wherein the enable means is responsive to the memory clock pulses, the rate control signal, and the first and second processor clock pulses for generating the first and second control signals.

Claim 25

The integrated microprocessor as defined in claim 22 wherein the outputs provided to the memory by the microprocessor include microprocessor access control signals, memory addresses, and data and wherein the inputs received by the microprocessor include memory access control signals and data.

Claim 26

The integrated microprocessor as defined in claim 23 wherein the microprocessor is arranged to be coupled to the memory by a plurality control lines, a data bus, and an address bus, wherein the microprocessor includes a plurality of output ports for providing the outputs onto the control lines, the data bus, and the address bus, and wherein the output ports include an output buffer arranged to be enabled by the first control signal for providing the outputs to the memory in synchronism with the memory clock pulses.

Claim 27

The integrated microprocessor as defined in claim 24 wherein the output buffers include a hard drive means for initially providing the outputs responsive to the first control signal and weak drive means for maintaining the outputs after termination of the first control signal.

Claim 28

The integrated microprocessor as defined in claim 25 wherein the output buffers include an input for receiving the levels of the outputs to be provided to the memory, wherein the microprocessor is arranged to provide the output levels to the output buffer inputs before the first control signal and wherein the output buffers include a latch coupled to the inputs for temporarily holding the levels at the inputs.

Claim 29

The integrated microprocessor as defined in claim 26 wherein the buffers include isolation means for isolating the inputs from the latches responsive to the first control signal to permit the levels at the inputs to be updated as the previous levels are provided to the memory.

Claim 30

The integrated microprocessor as defined in claim 27 wherein the output buffers are arranged to transfer the previous levels from the hard drive means to the weak drive means responsive to the termination of said first control signal prior to the input latches holding said updated output levels.

Claim 31

The integrated microprocessor as defined in claim 28 wherein the output buffers include a second latch for holding the transferred output levels and second isolation means for isolating the second latches from the updated levels responsive to the termination of the first control signal.

Claim 32

The integrated microprocessor as defined in claim 22 wherein the memory access controller includes at least one input for receiving an access control signal from the memory, the input including logic means responsive to the second control signal, the second phase portion of the memory clock pulses, and the first phase of the second processor clock pulses for receiving the external access control signal from the memory.

Claim 33

The integrated microprocessor as defined in claim 30 wherein the access control signal from the memory is a ready signal indicating successful completion of an access, and wherein the microprocessor is responsive to the ready signal for terminating the completed access.

Claim 34

The integrated microprocessor as defined in claim 31 wherein the memory access controller includes a state machine having at least first and second states, the second state for initiating and continuing an access to completion and the first state for terminating the completed access.

Claim 35

The integrated microprocessor as defined in claim 32 wherein the central processing unit provides an access request signal, wherein the memory access controller includes latch means for generating a pending request signal responsive to the access request signal, and wherein the state machine is responsive to the pending request signal, the second control signal, and being in the first state for sequencing to the second state upon the next first phase of the second processor clock pulses for initiating the access.

Claim 36

The integrated microprocessor as defined in claim 33 wherein the state machine is arranged for clearing the pending request signal from the latch means upon initiating the access.

Claim 37

The integrated microprocessor as defined in claim 34 wherein the memory access controller further includes ready means coupled to the logic means and being responsive to the ready signal for providing a qualified ready signal.

Claim 38

The integrated microprocessor as defined in claim 35 wherein the state machine is responsive to the qualified reading signal, the absence of the pending request signal, and being in the second state for sequencing to the first state upon the next first phase of the second processor clock pulses for terminating the completed external access.

Claim 39

In a computer system including a memory, a microprocessor, and a clock circuit, the memory coupled to the microprocessor by an address bus for executing load and store operations in synchronism with memory clock pulses at a first frequency, the memory clock pulses being provided to the microprocessor and the memory for controlling an accessing rate of the memory over the address bus, the clock circuit generating processor clock pulses at a second frequency for controlling a processing rate of the microprocessor, the second frequency being greater than the first frequency, the microprocessor comprising: a central processing unit coupled to the clock circuit, the central processing unit receiving the processor clock pulses and operating at the processing rate; and a bus interface unit coupled to the central processing unit and the address bus, the bus interface unit controlling when memory addresses are to be conveyed to the external memory over the bus to enable accessing of the memory, the bus interface unit being responsive to the memory clock pulses and the processor clock pulses for causing the memory address to be placed on the bus at the accessing rate while the central processing unit operates at the processing rate.

Claim 40

In a computer system including a memory, a microprocessor, and a clock circuit, the memory coupled to the microprocessor by an address bus for executing load and store operations in synchronism with memory clock pulses at a first frequency, the memory clock pulses being provided to the microprocessor and the memory for controlling an accessing rate of the memory over the address bus, the clock circuit generating processor clock pulses at a second frequency for controlling a processing rate of the microprocessor, the second frequency being greater than the first frequency, the microprocessor comprising: a central processing unit coupled to the clock circuit, the central processing unit receiving the processor clock pulses and operating at the processing rate; and a bus interface unit coupled to the central processing unit and the address bus, the bus interface unit controlling when memory addresses are to be conveyed to the external memory over the bus to enable accessing of the memory, the bus interface unit being responsive to the memory clock pulses and the processor clock pulses for causing the memory address to be placed on the bus at the accessing rate while the central processing unit operates at the processing rate.

Claim 41

The microprocessor as defined in claim 37 wherein the memory is an external memory.

Claim 42

The microprocessor as defined in claim 37 wherein the bus interface unit is coupled to the memory by a plurality of control lines and wherein a control means is arranged to cause the bus interface unit to provide the memory with first access control signals over selected ones of control lines when the memory clock pulses and the processor clock pulses are in a first predetermined phase relation to each other.

Claim 43

The microprocessor as defined in claim 39 wherein the bus interface unit is arranged for receiving second access control signals from the memory over selected ones of the control lines and wherein the control means is arranged to enable the bus interface unit to receive the second access control signals from the memory when the memory clock pulses and the processor clock pulses are in a second predetermined phase relation to each other.

Claim 44

The microprocessor as defined in claim 40 wherein the second frequency is predetermined multiple of the first frequency.

Claim 45

The microprocessor as defined in claim 41 wherein the memory clock pulses include a first phase portion and a second phase portion wherein the memory is arranged to receive the memory addresses and the first access control signals from the microprocessor during the first phase portion and to provide the second access control signals to the microprocessor during the second phase portion, and wherein the control means includes enable means for enabling the microprocessor to provide the addresses and first control signals to the memory during the first phase portion and for enabling the microprocessor to receive the second control signals from the memory during the second phase portion.

Claim 46

The microprocessor as defined in claim 42 wherein clock circuit is arranged for generating the clock pulses as first and second processor clock pulses, the first and second processor clock pulses being at the second frequency and having first and second clock pulse phases being of opposite phase relation, wherein the enable means is responsive to a rate control signal for enabling the microprocessor to provide the addresses and first control signals to the external memory upon the coincidence of each first clock pulse first phase and the memory clock pulse first phase portion and to receive the second control signals from the external memory upon the coincidence of each second clock pulse first phase and the memory clock pulse second phase portion.

Claim 47

The microprocessor as defined in claim 43 wherein the enable means is further responsive to the rate control signal for enabling the microprocessor to provide the addresses and first control signals to the external memory upon the coincidence of every other first clock pulse first phase and the memory clock pulse first phase portion and to receive the second control signals from the external memory upon the coincidence of every other second clock pulse first phase and the memory clock pulse second phase portion.

Claim 48

The microprocessor as defined in claim 44 when the enable means includes means for generating a drive output control signal for enabling the microprocessor to provide the addresses and first control signals to the memory and an enable input control signal for enabling the microprocessor to receive the second control signals from the memory.

Claim 51

The method of claim 46 wherein the computer system further includes a rate control input coupled to the microprocessor.

Claim 52

The method of claim 47 further comprising; receiving a rate control signal at the rate control input, the rate control signal being indicative of the relationship between the first frequency and the second frequency.

Claim 53

The method of claim 46 further comprising a step of: placing memory address on an address bus when the memory clock pulses and the processor clock pulses are in a first predetermined phase relationship to each other.

Claim 54

The method of claim 49 further comprising a step of: receiving control signals from the memory when the memory clock pulses and the processor clock pulses are in a second predetermined phase relationship to each other.

Claim 55

The method of claim 50 wherein the second frequency is a predetermined multiple of the first frequency.

Claim 56

The method of claim 51 wherein the first frequency differs from the second frequency by a multiple of two.

Claim 59

The method of claim 53 wherein the rate control signal is a bi-level signal capable of indicating that the microprocessor clock pulses are at twice the frequency of the memory clock pulses.

Claim 60

The method of claim 53 wherein the accessing step is performed by providing data to the external memory when the memory clock pulses and the processor clock pulses are in a first predetermined phase relationship to each other.

Claim 61

The method of claim 53 wherein the external memory is a cache memory.

Claim 62

The method of claim 53 wherein the external memory is a dynamic random access memory.

Claim 63

An output buffer for use in a microprocessor capable of operating at a processing rate for driving outputs to an external memory operating at an accessing rate over an external bus, the processing rate being greater than the accessing rate, the microprocessor operating at the processing rate while accessing the external memory at the accessing rate, said output buffer comprising: an input for receiving an input signal level; an output for driving said external bus with said levels of said input signals; a control input for receiving a control signal, said control input being coupled to said output for causing said output to drive said external bus with said level of said input signal responsive to said control signal; and isolating means coupled between said input and said output, and being coupled to said control input for isolating said input from said output in response to said control signal to enable said input to be updated with a new input signal level while said external bus is being driven with said input signal level.

Claim 64

An output buffer for use in a microprocessor capable of operating at a processing rate for driving outputs to an external memory operating at an accessing rate over an external bus, the processing rate being greater than the accessing rate, the microprocessor operating at the processing rate while accessing the external memory at the accessing rate, said output buffer comprising: an input for receiving an input signal level; an output for driving said external bus with said levels of said input signals; a control input for receiving a control signal, said control input being coupled to said output for causing said output to drive said external bus with said level of said input signal responsive to said control signal; and isolating means coupled between said input and said output, and being coupled to said control input for isolating said input from said output in response to said control signal to enable said input to be updated with a new input signal level while said external bus is being driven with said input signal level.

Claim 65

An output buffer as defined in claim 58 wherein said output includes a hard drive means for initially driving said bus with said level of said input signal responsive to said control signal and weak drive means for driving said bus with said level or said input signal after termination of said control signal.

Claim 66

An output buffer as defined in claim 59 wherein said output buffer further includes a first latch coupled between said isolation means and said output for temporarily holding said input level.

Claim 67

An output buffer as defined in claim 60 wherein said output buffer is arranged to transfer said input signal level from said hard drive means to said weak drive means responsive to the termination of said control signal.

Claim 68

An output buffer as defined in claim 61 wherein said output buffer includes a second latch for holding said transferred input level and second isolation means for isolating said second latch from said updated input level responsive to the termination of said control signal.

Claim 69

An output buffer for use in a microprocessor for driving outputs to an external memory over an external bus, the microprocessor capable of operating at a processing rate and the external memory operating at an accessing rate, the processing rate being greater than the accessing rate, the microprocessor operating at the processing rate while accessing the external memory at the accessing rate, the output buffer comprising: an input coupled to receive an input signal, the input signal having a current signal level and a previous signal level; a buffer output coupleable to the external bus; a control input coupled to the buffer output, the control input receiving a control signal; a first drive circuit including a first drive output coupled to the buffer output, the first drive circuit generating the current signal level at the first drive output to cause the buffer output to drive the external bus with the current signal level when the control signal is in a first state; a second drive circuit including a second drive output coupled to the buffer output, the second drive circuit generating the previous signal level at the second drive output to cause the buffer output to drive the external bus with the previous signal level when the control signal is in a second state; and an isolation circuit coupled between the input and the buffer output, and coupled to the control input, the isolation circuit isolating the input from the buffer output when the control signal is in a second state to enable the buffer output to drive the external bus at the previous input signal level without respect to the current input signal level.

Claim 70

An output buffer for use in a microprocessor for driving outputs to an external memory over an external bus, the microprocessor capable of operating at a processing rate and the external memory operating at an accessing rate, the processing rate being greater than the accessing rate, the microprocessor operating at the processing rate while accessing the external memory at the accessing rate, the output buffer comprising: an input coupled to receive an input signal, the input signal having a current signal level and a previous signal level; a buffer output coupleable to the external bus; a control input coupled to the buffer output, the control input receiving a control signal; a first drive circuit including a first drive output coupled to the buffer output, the first drive circuit generating the current signal level at the first drive output to cause the buffer output to drive the external bus with the current signal level when the control signal is in a first state; a second drive circuit including a second drive output coupled to the buffer output, the second drive circuit generating the previous signal level at the second drive output to cause the buffer output to drive the external bus with the previous signal level when the control signal is in a second state; and an isolation circuit coupled between the input and the buffer output, and coupled to the control input, the isolation circuit isolating the input from the buffer output when the control signal is in a second state to enable the buffer output to drive the external bus at the previous input signal level without respect to the current input signal level.

Claim 71

The output buffer as defined in claim 63 wherein the first drive circuit is configured to drive greater currents than the second drive circuit.

Claim 72

The output buffer of claim 64 wherein the output buffer further includes a first latch coupled between the isolation circuit and the buffer output, the first latch temporarily holding the current signal level.

Claim 73

The output buffer of claim 65 wherein the output buffer is arranged to transfer the current signal level from the first driving circuit to the second driving circuit when the control signal is in the first state.

Claim 74

The output buffer as defined in claim 66 wherein the output buffer includes a second latch for holding the current signal level after the current signal level is transferred from the first drive circuit and a second isolation circuit for isolating the second latch from the first latch when the control signal is in the second state.

Claim 75

A computing system for accessing an external memory operating at a slower clock rate than a microprocessor, the computing system comprising: a clock circuit producing clock pulses at an external memory accessing rate and at a processing clock rate, an integrated microprocessor coupled to the external memory and the clock circuit, operating at the processing clock rate, the integrated microprocessor being coupled to the external memory for synchronously loading data from and storing data in the external memory, whereby the integrated microprocessor continues to operate at the processing clock rate while the external memory is accessed at the memory accessing rate.

Claim 76

A computing system for accessing an external memory operating at a slower clock rate than a microprocessor, the computing system comprising: a clock circuit producing clock pulses at an external memory accessing rate and at a processing clock rate, an integrated microprocessor coupled to the external memory and the clock circuit, operating at the processing clock rate, the integrated microprocessor being coupled to the external memory for synchronously loading data from and storing data in the external memory, whereby the integrated microprocessor continues to operate at the processing clock rate while the external memory is accessed at the memory accessing rate.

Claim 77

The computing system of claim 68 wherein said processing clock rate is greater than said external memory accessing rate.

Claim 78

The computing system of claim 69 wherein said processing clock rate is an integer multiple of said external memory accessing rate.

Claim 79

The computing system of claim 70 wherein said processing clock rate is twice as high as said external memory accessing rate.

Claim 80

The computing system of claim 70 wherein said processing clock is three times higher than said external memory accessing rate.

Claim 81

The computing system of claim 70 wherein said processing clock rate is four times higher than said external memory accessing rate.

Claim 82

An integrated microprocessor arranged to access an external memory for executing load and store operations in synchronism with a memory clock which provides memory clock pulses at a first frequency for controlling the accessing rate of the external memory, said microprocessor comprising: an internal clock circuit, the internal clock circuit generating clock pulses at a second frequency for controlling a processing rate of said microprocessor, the second frequency being greater than the first frequency; and a central processing unit coupled to the internal clock and operating at the processing rate in response to the clock pulses at the second frequency; a memory access controller coupled to the memory and receiving the memory clock pulses, the memory access controller accessing the memory in synchronism with the memory clock pulses while the central processing unit is operating at the processing rate.

Claim 83

An integrated microprocessor arranged to access an external memory for executing load and store operations in synchronism with a memory clock which provides memory clock pulses at a first frequency for controlling the accessing rate of the external memory, said microprocessor comprising: an internal clock circuit, the internal clock circuit generating clock pulses at a second frequency for controlling a processing rate of said microprocessor, the second frequency being greater than the first frequency; and a central processing unit coupled to the internal clock and operating at the processing rate in response to the clock pulses at the second frequency; a memory access controller coupled to the memory and receiving the memory clock pulses, the memory access controller accessing the memory in synchronism with the memory clock pulses while the central processing unit is operating at the processing rate.

Claim 84

The integrated microprocessor as defined in claim 74 wherein a rate control signal indicates that the first frequency is related to the second frequency by a predetermined multiple of two.

Claim 85

The integrated microprocessor as defined in claim 75 wherein the rate control signal is a logical level one or a logical level zero.

Claim 86

The integrated microprocessor as defined in claim 74 wherein the memory clock pulses include a first phase portion and a second phase portion, wherein the memory is arranged to receive inputs from the microprocessor during the first phase portion and to provide outputs to the microprocessor during the second phase portion, and wherein the memory access controller includes enable means for enabling the microprocessor to provide outputs to the memory during the first phase portion and for enabling the microprocessor to receive inputs from the memory during said second phase portion.