Power-efficient external memory access control using external memory enable time durations independent of external memory accessing rate

Claim 2

In a processing system having a processor which accesses external memory for data and/or instructions at a plurality of external memory access rates including a maximum rate and a slow rate, said processor having a clock input and being responsive to a clock signal received at said clock input, an improved external memory access control system for reducing power consumption of said system by selectively accessing said memory at said slow rate, said control system comprising: clock means for providing a substantially constant-rate clock signal and coupled to said clock input for providing a variable-rate clock signal to said processor for establishing said slow rate; and enable duration control means coupled to said clock means for receiving said substantially constant-rate clock signal, said enable duration control means providing said external memory with external memory enable time duration control signals in response to said substantially constant-rate clock signal for establishing external memory enable time durations which are independent from said plurality of external memory access rates.

Claim 3

A control system as defined in claim 1 wherein said clock means includes a clock source having an output for providing a clock output and a divider having an input coupled to said clock source output and an output for providing said clock signal and wherein said enable duration control means has an input coupled between said clock source and said divider, said clock output being provided to said divider and said enable duration control means.

Claim 4

A control system as defined in claim 2 wherein said output of said divider is arranged to provide said external memory access rates including said maximum rate and said slow rate and wherein said enable duration control means is arranged to provide the same enable time duration for both said rates.

Claim 5

A control system as defined in claim 3 wherein said maximum rate is on the order of thirty-two times greater than said slow rate.

Claim 6

A control system as defined in claim 1 wherein said processing system comprises a plurality of external memories, wherein said processor includes a central processing unit for generating a first set of external memory addresses, and wherein said control system further comprises address decode logic means, coupled to said central processing unit and to said external memories for providing memory select signals to said external memories responsive to said first set of external memory addresses for selecting the memories to be accessed.

Claim 7

A control system as defined in claim 5 wherein said central processing unit further generates a second set of external memory addresses and is coupled to each of said external memories for conveying said second set of external memory addresses to said external memories.

Claim 8

A control system as defined in claim 6 wherein each of said external memories includes a plurality of memory locations, each said location having a unique address with respect to its external memory, wherein said memory select signals select the external memory to be accessed and wherein said second set of external memory addresses select the memory location to be accessed within said external memory to be accessed.

Claim 9

A control system as defined in claim 5 wherein said address decode logic means is external to said processor.

Claim 10

A control system as defined in claim 5 wherein said address decode logic means is within said processor.

Claim 11

A control system as defined in claim 5 wherein said clock means includes a clock source and a divider, said clock source being coupled to said divider, said divider having an output for providing said clock signal and wherein said enable duration control means includes an input coupled between said clock source and said divider.

Claim 12

A control system as defined in claim 10 wherein said clock source is external to said processor.

Claim 13

A control system as defined in claim 11 wherein said divider is within said processor.

Claim 14

A control system as defined in claim 12 wherein said enable duration control means is within said processor.

Claim 15

A control system as defined in claim 5 wherein said processing system includes a bus coupled between said central processing unit and said external memories for conveying said data or instructions between said central processing unit and said external memories during said memory accesses.

Claim 16

A control system as defined in claim 14 wherein said enable duration control means include an output coupled to said external memories for providing said external memories with said external memory enable time duration control signals for enabling said memories to utilize said bus during said enable time durations.

Claim 17

A control system as defined in claim 15 wherein said enable duration control means output is coupled directly to said external memories.

Claim 18

A control system as defined in claim 15 wherein said enable duration control means output is coupled to said external memories through said address decode logic means.

Claim 19

A memory access control system for controlling memory enable times of a memory independently from memory access rate, said memory access control system comprising: clock means for providing a variable-rate clock signal for establishing memory access rates including a maximum rate and a slow rate and a substantially constant-rate clock signal; and memory enable duration control means having an input coupled to said clock means and an output coupled to said memory and responsive to said substantially constant-rate clock signal for providing said memory with enable signals having a fixed duration corresponding to said maximum rate regardless of the memory access rate provided by said clock means.

Claim 20

A memory access control system for controlling memory enable times of a memory independently from memory access rate, said memory access control system comprising: clock means for providing a variable-rate clock signal for establishing memory access rates including a maximum rate and a slow rate and a substantially constant-rate clock signal; and memory enable duration control means having an input coupled to said clock means and an output coupled to said memory and responsive to said substantially constant-rate clock signal for providing said memory with enable signals having a fixed duration corresponding to said maximum rate regardless of the memory access rate provided by said clock means.

Claim 21

A memory access control system as defined in claim 19 wherein said clock means comprises a clock source for providing clock signals for establishing said maximum rate and a divider coupled to said clock source for dividing said clock signals for providing said slow rate, and wherein said memory enable duration control means has an input coupled between said clock source and said divider.

Claim 22

A processing system comprising: clock means for providing a substantially constant-rate clock signal and a variable-rate clock signal; a memory having a bus enable input, an address input and an output, the memory providing data and/or instructions at said output in response to an address signal received at said address input and a bus enable signal received at said bus enable input; a processor coupled to the memory, the processor providing an address to said memory address input to access said memory for said data and/or instructions, said processor having a clock input coupled to said clock means for receiving said variable-rate clock signal, the processor being responsive to said variable-rate clock signal for providing said address, said variable-rate clock signal establishing an external memory access rate; and enable duration control means having an input coupled to said clock means and an output coupled to the bus enable input, the enable duration control means providing a bus enable signal to said bus enable input in response to said substantially constant-rate clock signal, said bus enable signal having a substantially constant external memory enable time duration, the external memory enable time duration being independent of said external memory access rate.

Claim 23

A processing system comprising: clock means for providing a substantially constant-rate clock signal and a variable-rate clock signal; a memory having a bus enable input, an address input and an output, the memory providing data and/or instructions at said output in response to an address signal received at said address input and a bus enable signal received at said bus enable input; a processor coupled to the memory, the processor providing an address to said memory address input to access said memory for said data and/or instructions, said processor having a clock input coupled to said clock means for receiving said variable-rate clock signal, the processor being responsive to said variable-rate clock signal for providing said address, said variable-rate clock signal establishing an external memory access rate; and enable duration control means having an input coupled to said clock means and an output coupled to the bus enable input, the enable duration control means providing a bus enable signal to said bus enable input in response to said substantially constant-rate clock signal, said bus enable signal having a substantially constant external memory enable time duration, the external memory enable time duration being independent of said external memory access rate.

Claim 24

A processing system as defined in claim 20 wherein said clock means includes a clock source having an output for providing said substantially constant-rate clock signal and a divider having an input coupled to said clock source output and an output for providing said variable-rate clock signal and wherein said enable duration control means input is coupled to said clock source output.

Claim 25

A processing system as defined in claim 20 wherein said memory comprises a plurality of external memory devices, each respective external memory device having a respective bus enable input and a respective address input, and wherein said processor includes a central processing unit for generating a first set of external memory addresses, and wherein said processing system further comprises address decode logic means coupled to said central processing unit and to said plurality of external memory devices for providing memory select signals to one said respective address input respective to said first set of external memory addresses.

Claim 26

A processing system as defined in claim 22 wherein each external memory device has a respective output and wherein said processing system includes a bus coupled between said central processing unit and each said respective output for conveying said data and/or instructions between said central processing unit and said plurality of external memory devices.

Claim 27

A processing system as defined in claim 23 wherein said each respective external memory device utilizes said bus during said external memory enable time duration in response to said bus enable signal.