Method and apparatus for analyzing failure of semiconductor wafer

Claim 1

A method for analyzing the failure of a semiconductor wafer comprising: a first step of checking the pattern defect of said semiconductor wafer to make a pattern defect map which represents the distribution of the pattern defects at each process of semiconductor manufacture; a second step of making a fail bit map which represents the distribution of electrical defects after said each process of semiconductor manufacture is completed; and a third step of specifying a process at which a pattern defect that causes said electrical defects is generated by comparing said pattern defect map made at said first step with said fail bit map made at said second step, said third step including the step of retrieving pattern defects on a first pattern defect map made at the (n-1)th process and a second pattern defect map made at the n-th process to decide that all the pattern defects detected on said second pattern defect map in a predetermined region within a predetermined distance from the position of each pattern defect detected on said first pattern defect map are generated at a process prior to the (n-1)th process, and that pattern defects detected on said second pattern defect map in other regions than said each predetermined region are generated at said n-th process.

Claim 2

A method for analyzing the failure of a semiconductor wafer comprising: a first step of checking the pattern defect of said semiconductor wafer to make a pattern defect map which represents the distribution of the pattern defects at each process of semiconductor manufacture; a second step of making a fail bit map which represents the distribution of electrical defects after said each process of semiconductor manufacture is completed; and a third step of specifying a process at which a pattern defect that causes said electrical defects is generated by comparing said pattern defect map made at said first step with said fail bit map made at said second step, said third step including the step of retrieving pattern defects on a first pattern defect map made at the (n-1)th process and a second pattern defect map made at the n-th process to decide that all the pattern defects detected on said second pattern defect map in a predetermined region within a predetermined distance from the position of each pattern defect detected on said first pattern defect map are generated at a process prior to the (n-1)th process, and that pattern defects detected on said second pattern defect map in other regions than said each predetermined region are generated at said n-th process.

Claim 3

A method for analyzing the failure of a semiconductor wafer comprising: a first step of checking the pattern failure of said semiconductor wafer to make a pattern defect map which represents the distribution of the pattern defects at each process of semiconductor manufacture; a second step of making a fail bit map which represents the distribution of electrical defects after said each process of semiconductor manufacture is completed; and a third step of specifying a process at which a pattern defect that causes said electrical defects is generated by comparing said pattern defect map made at said first step with said fail bit map made at said second step, said third step including the step of retrieving pattern defects on a first pattern defect map made at the (n-1)th process and a second pattern defect map made at the n-th process respectively to decide that the pattern defects on said second pattern defect map which are not detected on said first pattern defect map in each predetermined region within a predetermined distance from the position of said pattern defect detected on said second pattern defect map are generated at the n-th process, and that said pattern defects on said second pattern defect map detected on said first pattern defect map in said each predetermined region are generated at a process, prior to said (n-1)th process.

Claim 4

A method for analyzing the failure of a semiconductor wafer comprising: a first step of checking the pattern failure of said semiconductor wafer to make a pattern defect map which represents the distribution of the pattern defects at each process of semiconductor manufacture; a second step of making a fail bit map which represents the distribution of electrical defects after said each process of semiconductor manufacture is completed; and a third step of specifying a process at which a pattern defect that causes said electrical defects is generated by comparing said pattern defect map made at said first step with said fail bit map made at said second step, said third step including the step of retrieving pattern defects on a first pattern defect map made at the (n-1)th process and a second pattern defect map made at the n-th process respectively to decide that the pattern defects on said second pattern defect map which are not detected on said first pattern defect map in each predetermined region within a predetermined distance from the position of said pattern defect detected on said second pattern defect map are generated at the n-th process, and that said pattern defects on said second pattern defect map detected on said first pattern defect map in said each predetermined region are generated at a process, prior to said (n-1)th process.

Claim 5

A method for analyzing the failure of a semiconductor wafer comprising: a first step of checking the pattern defect of said semiconductor wafer to make a pattern defect map which represents the distribution of the pattern defects at each process of semiconductor manufacture; a second step of making a fail bit map which represents the distribution of electrical defects after said each process of semiconductor manufacture is completed; and a third step of specifying a process at which a pattern defect that causes said electrical defects is generated by comparing said pattern defect map made at said first step with said fail bit map made at said second step, said third step including the step of retrieving the pattern defects on said pattern defect map to merge, as a pattern defect, one of a plurality of pattern defects and other pattern defects detected in a region within a distance of 0.25 to 1.5 μm from said pattern defect if said plurality of pattern defects are detected.

Claim 6

A method for analyzing the failure of a semiconductor wafer comprising: a first step of checking the pattern defect of said semiconductor wafer to make a pattern defect map which represents the distribution of the pattern defects at each process of semiconductor manufacture; a second step of making a fail bit map which represents the distribution of electrical defects after said each process of semiconductor manufacture is completed; and a third step of specifying a process at which a pattern defect that causes said electrical defects is generated by comparing said pattern defect map made at said first step with said fail bit map made at said second step, said third step including the step of retrieving the pattern defects on said pattern defect map to merge, as a pattern defect, one of a plurality of pattern defects and other pattern defects detected in a region within a distance of 0.25 to 1.5 μm from said pattern defect if said plurality of pattern defects are detected.

Claim 7

A method for analyzing the failure of a semiconductor wafer comprising: a first step of checking the pattern defect of said semiconductor wafer to make a pattern defect map which represents the distribution of the pattern defects at each process of semiconductor manufacture; a second step of making a fail bit map which represents the distribution of electrical defects after said each process of semiconductor manufacture is completed; and a third step of specifying a process at which a pattern defect that causes said electrical defects is generated by comparing said pattern defect map made at said first step with said fail bit map made at said second step, said third step including the step of deciding that a pattern defect located closest to the central line of a line failure portion having a plurality of continuous failed bits, which is detected in a region within a predetermined distance from said central line of said line failure portion on said pattern defect map, causes the generation of said line failure portion if said line failure portion is detected on said fail bit map.

Claim 8

A method for analyzing the failure of a semiconductor wafer comprising: a first step of checking the pattern defect of said semiconductor wafer to make a pattern defect map which represents the distribution of the pattern defects at each process of semiconductor manufacture; a second step of making a fail bit map which represents the distribution of electrical defects after said each process of semiconductor manufacture is completed; and a third step of specifying a process at which a pattern defect that causes said electrical defects is generated by comparing said pattern defect map made at said first step with said fail bit map made at said second step, said third step including the step of deciding that a pattern defect located closest to the central line of a line failure portion having a plurality of continuous failed bits, which is detected in a region within a predetermined distance from said central line of said line failure portion on said pattern defect map, causes the generation of said line failure portion if said line failure portion is detected on said fail bit map.

Claim 9

A method for analyzing the failure of a semiconductor wafer comprising: a first step of checking the pattern defect of said semiconductor wafer to make a pattern defect map which represents the distribution of the pattern defects at each process of semiconductor manufacture; a second step of making a fail bit map which represents the distribution of electrical defects after said each process of semiconductor manufacture is completed; and a third step of specifying a process at which a pattern defect that causes said electrical defects is generated by comparing said pattern defect map made at said first step with said fail bit map made at said second step, said third step including the steps of: obtaining, in advance, the relationship between the size of a pattern defect and a probability that a pattern defect causes electrical defects; and multiplying a distance between a plurality of pattern defects detected in a region within a predetermined distance from the center of a failed bit on said fail bit map or the central line of a line failure portion formed by a plurality of continuous failed bits and said center of said failed bit or said central line of said line failure portion by an inverse number of said probability corresponding to said size of said pattern defect detected in said region within a predetermined distance so as to find corrected distances respectively and to decide that a pattern defect corresponding to said corrected distance having the smallest value causes electrical defects.

Claim 10

A method for analyzing the failure of a semiconductor wafer comprising: a first step of checking the pattern defect of said semiconductor wafer to make a pattern defect map which represents the distribution of the pattern defects at each process of semiconductor manufacture; a second step of making a fail bit map which represents the distribution of electrical defects after said each process of semiconductor manufacture is completed; and a third step of specifying a process at which a pattern defect that causes said electrical defects is generated by comparing said pattern defect map made at said first step with said fail bit map made at said second step, said third step including the steps of: obtaining, in advance, the relationship between the size of a pattern defect and a probability that a pattern defect causes electrical defects; and multiplying a distance between a plurality of pattern defects detected in a region within a predetermined distance from the center of a failed bit on said fail bit map or the central line of a line failure portion formed by a plurality of continuous failed bits and said center of said failed bit or said central line of said line failure portion by an inverse number of said probability corresponding to said size of said pattern defect detected in said region within a predetermined distance so as to find corrected distances respectively and to decide that a pattern defect corresponding to said corrected distance having the smallest value causes electrical defects.

Claim 11

An apparatus for analyzing the failure of a semiconductor wafer comprising: pattern defect map making means for checking the pattern defect of said semiconductor wafer to make a pattern defect map which represents the distribution of the pattern defects at each process of semiconductor manufacture; fail bit map making means for making a fail bit map which represents the distribution of electrical defects after said each process of semiconductor manufacture is completed; and pattern defect generation step specifying means for specifying a process at which a pattern defect that causes said electrical defects is generated by comparing said pattern defect map made by said pattern defect map making means with said fail bit map made by said fail bit map making means, said pattern defect generation step specifying means including: means for retrieving pattern defects on a first pattern defect map made at the (n-1)th process and a second pattern defect map made at the n-th process respectively; and means for deciding that all the pattern defects detected on said second pattern defect map in each predetermined region within a predetermined distance from the position of each pattern defect detected on said first pattern defect map are generated at a process prior to the (n-1)th process, and that pattern defects detected on said second pattern defect map in other regions than said each predetermined region are generated at said n-th process.

Claim 12

An apparatus for analyzing the failure of a semiconductor wafer comprising: pattern defect map making means for checking the pattern defect of said semiconductor wafer to make a pattern defect map which represents the distribution of the pattern defects at each process of semiconductor manufacture; fail bit map making means for making a fail bit map which represents the distribution of electrical defects after said each process of semiconductor manufacture is completed; and pattern defect generation step specifying means for specifying a process at which a pattern defect that causes said electrical defects is generated by comparing said pattern defect map made by said pattern defect map making means with said fail bit map made by said fail bit map making means, said pattern defect generation step specifying means including: means for retrieving pattern defects on a first pattern defect map made at the (n-1)th process and a second pattern defect map made at the n-th process respectively; and means for deciding that all the pattern defects detected on said second pattern defect map in each predetermined region within a predetermined distance from the position of each pattern defect detected on said first pattern defect map are generated at a process prior to the (n-1)th process, and that pattern defects detected on said second pattern defect map in other regions than said each predetermined region are generated at said n-th process.

Claim 13

An apparatus for analyzing the failure of a semiconductor wafer comprising: pattern defect map making means for checking the pattern defect of said semiconductor wafer to make a pattern defect map which represents the distribution of the pattern defects at each process of semiconductor manufacture; fail bit map making means for making a fail bit map which represents the distribution of electrical defects after said each process of semiconductor manufacture is completed; and pattern defect generation step specifying means for specifying a process at which a pattern defect that causes said electrical defects is generated by comparing said pattern defect map made by said pattern defect map making means with said fail bit map made by said fail bit map making means, said pattern defect generation step specifying means including: means for retrieving pattern defects on a first pattern defect map made at the (n-1)th process and a second pattern defect map made at the n-th process respectively; and means for deciding that pattern defects on said second pattern defect map which are not detected on said first pattern defect map in each predetermined region within a predetermined distance from the position of said pattern defect detected on said second pattern defect map are generated at the n-th process, and that the pattern defects on said second pattern defect map detected on said first pattern defect map in said each predetermined region are generated at a process prior to said (n-1)th process.

Claim 14

An apparatus for analyzing the failure of a semiconductor wafer comprising: pattern defect map making means for checking the pattern defect of said semiconductor wafer to make a pattern defect map which represents the distribution of the pattern defects at each process of semiconductor manufacture; fail bit map making means for making a fail bit map which represents the distribution of electrical defects after said each process of semiconductor manufacture is completed; and pattern defect generation step specifying means for specifying a process at which a pattern defect that causes said electrical defects is generated by comparing said pattern defect map made by said pattern defect map making means with said fail bit map made by said fail bit map making means, said pattern defect generation step specifying means including: means for retrieving pattern defects on a first pattern defect map made at the (n-1)th process and a second pattern defect map made at the n-th process respectively; and means for deciding that pattern defects on said second pattern defect map which are not detected on said first pattern defect map in each predetermined region within a predetermined distance from the position of said pattern defect detected on said second pattern defect map are generated at the n-th process, and that the pattern defects on said second pattern defect map detected on said first pattern defect map in said each predetermined region are generated at a process prior to said (n-1)th process.

Claim 15

An apparatus for analyzing the failure of a semiconductor wafer comprising: pattern defect map making means for checking the pattern defect of said semiconductor wafer to make a pattern defect map which represents the distribution of the pattern defects at each process of semiconductor manufacture; fail bit map making means for making a fail bit map which represents the distribution of electrical defects after said each process of semiconductor manufacture is completed; and pattern defect generation step specifying means for specifying a process at which a pattern defect that causes said electrical defects is generated by comparing said pattern defect map made by said pattern defect map making means with said fail bit map made by said fail bit map making means, said pattern defect generation step specifying means including means for retrieving pattern defects on said pattern defect map to merge, as a pattern defect, one of a plurality of pattern defects and other pattern defects detected in a region within a distance of 0.25 to 1.5 μm from said pattern defect if said plurality of pattern defects are detected.

Claim 16

An apparatus for analyzing the failure of a semiconductor wafer comprising: pattern defect map making means for checking the pattern defect of said semiconductor wafer to make a pattern defect map which represents the distribution of the pattern defects at each process of semiconductor manufacture; fail bit map making means for making a fail bit map which represents the distribution of electrical defects after said each process of semiconductor manufacture is completed; and pattern defect generation step specifying means for specifying a process at which a pattern defect that causes said electrical defects is generated by comparing said pattern defect map made by said pattern defect map making means with said fail bit map made by said fail bit map making means, said pattern defect generation step specifying means including means for retrieving pattern defects on said pattern defect map to merge, as a pattern defect, one of a plurality of pattern defects and other pattern defects detected in a region within a distance of 0.25 to 1.5 μm from said pattern defect if said plurality of pattern defects are detected.

Claim 17

An apparatus for analyzing the failure of a semiconductor wafer comprising: pattern defect map making means for checking the pattern defect of said semiconductor wafer to make a pattern defect map which represents the distribution of the pattern defects at each process of semiconductor manufacture; fail bit map making means for making a fail bit map which represents the distribution of electrical defects after said each process of semiconductor manufacture is completed; and pattern defect generation step specifying means for specifying a process at which a pattern defect that causes said electrical defects is generated by comparing said pattern defect map made by said pattern defect map making means with said fail bit map made by said fail bit map making means, said pattern defect generation step specifying means including means for deciding that a pattern defect located closest to the central line of a line failure portion having a plurality of continuous failed bits, which is detected in a region within a predetermined distance from said central line of said line failure portion on said pattern defect map, causes the generation of said line failure portion if said line failure portion is detected on said fail bit map.

Claim 18

An apparatus for analyzing the failure of a semiconductor wafer comprising: pattern defect map making means for checking the pattern defect of said semiconductor wafer to make a pattern defect map which represents the distribution of the pattern defects at each process of semiconductor manufacture; fail bit map making means for making a fail bit map which represents the distribution of electrical defects after said each process of semiconductor manufacture is completed; and pattern defect generation step specifying means for specifying a process at which a pattern defect that causes said electrical defects is generated by comparing said pattern defect map made by said pattern defect map making means with said fail bit map made by said fail bit map making means, said pattern defect generation step specifying means including means for deciding that a pattern defect located closest to the central line of a line failure portion having a plurality of continuous failed bits, which is detected in a region within a predetermined distance from said central line of said line failure portion on said pattern defect map, causes the generation of said line failure portion if said line failure portion is detected on said fail bit map.

Claim 19

An apparatus for analyzing the failure of a semiconductor wafer comprising: pattern defect map making means for checking the pattern defect of said semiconductor wafer to make a pattern defect map which represents the distribution of the pattern defects at each process of semiconductor manufacture; fail bit map making means for making a fail bit map which represents the distribution of electrical defects after said each process of semiconductor manufacture is completed; and pattern defect generation step specifying means for specifying a process at which a pattern defect that causes said electrical defects is generated by comparing said pattern defect map made by said pattern defect map making means with said fail bit map made by said fail bit map making means, said pattern defect generation step specifying means including: means for obtaining, in advance, the relationship between the size of a pattern defect and a probability that a pattern defect causes electrical defects; and means for multiplying a distance between a plurality of pattern defects detected in a region within a predetermined distance from the center of a failed bit on said fail bit map or the central line of a line failure portion formed by a plurality of continuous failed bits and said center of said failed bit or said central line of said line failure portion by an inverse number of said probability corresponding to said size of said pattern defect detected in said region within a predetermined distance so as to find corrected distances respectively and to decide that a pattern defect corresponding to said corrected distance having the smallest value causes electrical defects.

Claim 20

An apparatus for analyzing the failure of a semiconductor wafer comprising: pattern defect map making means for checking the pattern defect of said semiconductor wafer to make a pattern defect map which represents the distribution of the pattern defects at each process of semiconductor manufacture; fail bit map making means for making a fail bit map which represents the distribution of electrical defects after said each process of semiconductor manufacture is completed; and pattern defect generation step specifying means for specifying a process at which a pattern defect that causes said electrical defects is generated by comparing said pattern defect map made by said pattern defect map making means with said fail bit map made by said fail bit map making means, said pattern defect generation step specifying means including: means for obtaining, in advance, the relationship between the size of a pattern defect and a probability that a pattern defect causes electrical defects; and means for multiplying a distance between a plurality of pattern defects detected in a region within a predetermined distance from the center of a failed bit on said fail bit map or the central line of a line failure portion formed by a plurality of continuous failed bits and said center of said failed bit or said central line of said line failure portion by an inverse number of said probability corresponding to said size of said pattern defect detected in said region within a predetermined distance so as to find corrected distances respectively and to decide that a pattern defect corresponding to said corrected distance having the smallest value causes electrical defects.