MOS structure device having asymmetric LDD structure and fabrication method thereof

Claim 2

An MOS semiconductor device containing an MOSFET, said device comprising: a semiconductor substrate of a first conductivity type; a first heavily doped region of a second conductivity type opposite to said first conductivity type, said first heavily doped region being formed in a surface area of said substrate; a lightly doped region of said second conductivity type formed in said surface area of said substrate, said lightly doped region being adjacent to said first heavily doped region; said first heavily doped region and said lightly doped region acting as a drain region of said MOSFET; a second heavily doped region of said second conductivity type formed in said surface area of said substrate apart from said first heavily doped region and said lightly doped region; said second heavily doped region acting as a source region of said MOSFET; a channel region being formed between a source-side end of said lightly doped region and a drain-side end of said second heavily doped region; said first heavily doped region, said second heavily doped region and said lightly doped region constituting an asymmetric LDD structure; a gate insulator film formed on said surface area of said substrate to cover said first heavily doped region, said second heavily doped region and said lightly doped region; a gate electrode formed on said gate insulator film to be positioned over said channel region, said gate electrode being composed of a plurality of parts; a first part of said plurality of parts having a drain-side end positioned over said lightly doped region and a source-side end positioned over said channel region not to extend to said second heavily doped region; and a second part of said plurality of parts being formed on and in contact with said first part and said gate insulator film.

Claim 3

The device as claimed in claim 1, wherein a position of said lightly doped region is dependent upon a position of said first part of said plurality of parts of said gate electrode.

Claim 4

The device as claimed in claim 1, wherein said first part of said plurality of parts of said gate electrode is made of a patterned polysilicon film, and said second part of said plurality of parts is made of one of (a) a patterned polysilicon film, (b) a patterned refractory-metal silicide film, and (c) a combination of a patterned polysilicon film and a patterned refractory-metal silicide film.

Claim 5

The device as claimed in claim 1, wherein said drain-side end of said second part of said plurality of parts is positioned right over said drain-side end of said first part of said plurality of parts.

Claim 6

The device as claimed in claim 1, further comprising first and second sidewall spacers formed on said gate insulator film, said first sidewall spacer being placed on a drain side of said gate electrode and said second sidewall spacer being placed on a source side of said gate electrode; and wherein said drain-side end of said second part of said plurality of parts is positioned right over said drain-side end of said first part of said plurality of parts.

Claim 7

The device as claimed in claim 1, further comprising another MOSFET having a symmetric LDD structure, wherein said first heavily doped region is commonly used for said MOSFET having said symmetric LDD structure.

Claim 8

An MOS semiconductor device containing first and second MOSFETs, said first and second MOSFET's each having an asymmetric LDD structure, said device comprising; a semiconductor substrate of a first conductivity type; a first heavily doped region of a second conductivity type opposite to said first conductivity type, said first heavily doped region being formed in a surface area of said substrate; first and second lightly doped regions of said second conductivity type formed in said surface area of said substrate, said first lightly doped region being adjacent to one side of said first heavily doped region and said second lightly doped region being adjacent to another side thereof; said first heavily doped region and said first lightly doped region acting as a drain region of said first MOSFET, and said first heavily doped region and said second lightly doped region acting as a drain region of said second MOSFET; a second heavily doped region of said second conductivity type formed in said surface area of said substrate apart from said first heavily doped region and said lightly doped region; said second heavily doped region acting as a source region of said first MOSFET; a third heavily doped region of said second conductivity type formed in said surface area of said substrate, said third heavily doped region acting as a source region of said second-MOSFET; a first channel region for said first MOSFET being formed between a source-side end of said first lightly doped region and a drain-side end of said second heavily doped region; a second channel region for said second MOSFET being formed between a source-side end of said second lightly doped region and a drain-side end of said third heavily doped region; said first heavily doped region, said second heavily doped region and said first lightly doped region constituting an asymmetric LDD structure for said first MOSFET, and said first heavily doped region, said third heavily doped region and said second lightly doped region constituting an asymmetric LDD structure for said second MOSFET; a gate insulator film formed on said surface area of said substrate to cover said first heavily doped region, said second heavily doped region, said first lightly doped region and said second lightly doped region; a first gate electrode formed on said gate insulator film to be positioned over said first channel region, said first gate electrode being composed of a plurality of parts, a first part of said plurality of parts having a drain-side end positioned over said first lightly doped region and a source-side end positioned over said first channel region not to extend to said second heavily doped region, a second part of said plurality of parts being formed on and in contact with said first part and said gate insulator film; and a second gate electrode formed on said gate insulator film to be positioned over said second channel region, said second gate electrode being composed of a plurality of parts, a first part of said plurality of parts having a drain-side end positioned over said second lightly doped region and a source-side end positioned over said second channel region not to extend to said third heavily doped region, a second part of said plurality of parts being formed on and in contact with said first part and said gate insulator film.

Claim 9

An MOS semiconductor device containing first and second MOSFETs, said first and second MOSFET's each having an asymmetric LDD structure, said device comprising; a semiconductor substrate of a first conductivity type; a first heavily doped region of a second conductivity type opposite to said first conductivity type, said first heavily doped region being formed in a surface area of said substrate; first and second lightly doped regions of said second conductivity type formed in said surface area of said substrate, said first lightly doped region being adjacent to one side of said first heavily doped region and said second lightly doped region being adjacent to another side thereof; said first heavily doped region and said first lightly doped region acting as a drain region of said first MOSFET, and said first heavily doped region and said second lightly doped region acting as a drain region of said second MOSFET; a second heavily doped region of said second conductivity type formed in said surface area of said substrate apart from said first heavily doped region and said lightly doped region; said second heavily doped region acting as a source region of said first MOSFET; a third heavily doped region of said second conductivity type formed in said surface area of said substrate, said third heavily doped region acting as a source region of said second-MOSFET; a first channel region for said first MOSFET being formed between a source-side end of said first lightly doped region and a drain-side end of said second heavily doped region; a second channel region for said second MOSFET being formed between a source-side end of said second lightly doped region and a drain-side end of said third heavily doped region; said first heavily doped region, said second heavily doped region and said first lightly doped region constituting an asymmetric LDD structure for said first MOSFET, and said first heavily doped region, said third heavily doped region and said second lightly doped region constituting an asymmetric LDD structure for said second MOSFET; a gate insulator film formed on said surface area of said substrate to cover said first heavily doped region, said second heavily doped region, said first lightly doped region and said second lightly doped region; a first gate electrode formed on said gate insulator film to be positioned over said first channel region, said first gate electrode being composed of a plurality of parts, a first part of said plurality of parts having a drain-side end positioned over said first lightly doped region and a source-side end positioned over said first channel region not to extend to said second heavily doped region, a second part of said plurality of parts being formed on and in contact with said first part and said gate insulator film; and a second gate electrode formed on said gate insulator film to be positioned over said second channel region, said second gate electrode being composed of a plurality of parts, a first part of said plurality of parts having a drain-side end positioned over said second lightly doped region and a source-side end positioned over said second channel region not to extend to said third heavily doped region, a second part of said plurality of parts being formed on and in contact with said first part and said gate insulator film.

Claim 10

The device as claimed in claim 7, wherein a position of said first lightly doped region is dependent upon a position of said first part of said plurality of parts of said first gate electrode, and a position of said second lightly doped region is dependent upon a position of said first part of said plurality of parts of said second gate electrode.

Claim 11

The device as claimed in claim 7, wherein said first part of said plurality of parts of said first gate electrode is made of a patterned polysilicon film, and said second part of said plurality of parts is made of one of (a) a patterned polysilicon film, (b) a patterned refractory-metal silicide film, and (c) a combination of a patterned polysilicon film and a patterned refractory-metal silicide film; and wherein said first part of said plurality of parts of said second gate electrode is made of a patterned polysilicon film, and said second part of said plurality of parts is made of one of (a) a patterned polysilicon film, (b) a patterned refractory-metal silicide film, and (c) a combination of a patterned polysilicon film and a patterned refractory-metal silicide film.

Claim 12

The device as claimed in claim 7, wherein a drain-side end of said second part of said plurality of parts of said first gate electrode is positioned right over said drain-side end of said first part of said plurality of parts of said first gate electrode; and wherein a drain-side end of said first part of said plurality of parts of said second gate electrode is positioned right over said drain-side end of said first part of said plurality of parts of said second gate electrode.

Claim 13

The device as claimed in claim 7, further comprising first, second, third and fourth sidewall spacers formed on said gate insulator film; wherein said first sidewall spacer is placed on a drain side of said first gate electrode, said second sidewall spacer is placed on a source side of said first gate electrode, said third sidewall spacer is placed on a drain side of said second gate electrode, and said fourth sidewall spacer is placed on a source side of said second gate electrode; and wherein a drain-side end of said second part of said plurality of parts of said first gate electrode is positioned right over said drain-side end of said first part of said plurality of parts of said first gate electrode; and wherein a drain-side end of said second part of said plurality of parts of said second gate electrode is positioned right over said drain-side end of said first part of said plurality of parts of said second gate electrode.