Semiconductor device having a nonvolatile memory cell in which the floating gate is charged with hot charge carriers at the source side

Claim 2

A semiconductor device with a semiconductor body having a surface, a memory element at said surface comprising a field effect transistor with a source zone and a drain zone, each separated from a surrounding portion of the semiconductor body by a pn-junction, a channel region situated between the source and drain zones, a control electrodes, a floating gate electrode situated between the control electrode and the channel region, a gate dielectric separating the floating gate electrode from the surface, and means for providing charge, on the floating gate electrode at or adjacent the source zone through generation of hot charge carriers, characterized in that: said means comprise a thickened portion of the gate dielectric adjoining the source zone, while the pn-junction of the source zone intersects the surface of the semiconductor body below the thickened portion, the source zone and the floating gate electrode have edges extending toward the surface which coincide at least substantially, and the gate dielectric at the area where the pn-junction of the drain zone intersects the surface is thinner than the gate dielectric at the area of the thickened portion.

Claim 3

A semiconductor device as claimed in claim 1, characterized in that the semiconductor body is made of silicon, the dielectric layer of silicon oxide, and the floating gate electrode of silicon, while the thickened portion of the gate dielectric is formed by an oxide layer which is obtained at least partly through thermal oxidation of silicon material at the area of the source zone.

Claim 4

A semiconductor device as claimed in claim 2, characterized in that the gate dielectric and the floating gate electrode extend to above the drain zone, while the gate dielectric has a second thickened portion which is situated above the drain zone and, at the surface, is at a distance from the channel.

Claim 5

A semiconductor device as claimed in claim 3, characterized in that the drain zone includes with an extension which extends under the second thickened portion up to the channel region.

Claim 6

A semiconductor device as claimed in claims 1, characterized in that the gate dielectric at the drain side of the channel has a thickness such that information stored on the floating gate electrode can be erased through tunnelling of charge carriers between the floating gate electrode and the drain zone.

Claim 7

A non-volatile memory device comprising a number of memory elements, each memory element comprising a field effect transistor with a source zone and a drain zone, each separated from a surrounding portion of the semiconductor body by a pn-junction, and with a channel region situated between the source and drain zones, a control electrode and a floating gate electrode situated between the control electrode and the channel region, a gate dielectric separating the floating electrode from the surface and means for providing charge on the floating gate electrode at or adjacent the source zone through generation of hot charge carriers, characterized in that: said means comprise a thickened portion of the gate dielectric adjoining the source zone, while the pn-junction of the source zone intersects the surface of the semiconductor body below the thickened portion, the source zone and the floating gate electrode, seen at the surface, have edges which coincide at least substantially, and the gate dielectric at the area where the pn-junction of the drain zone intersects the surface is thinner than the gate dielectric at the area of the thickened portion, said memory elements being arranged in a system of rows and columns in a common semiconductor body.

Claim 8

A non-volatile memory device comprising a number of memory elements, each memory element comprising a field effect transistor with a source zone and a drain zone, each separated from a surrounding portion of the semiconductor body by a pn-junction, and with a channel region situated between the source and drain zones, a control electrode and a floating gate electrode situated between the control electrode and the channel region, a gate dielectric separating the floating electrode from the surface and means for providing charge on the floating gate electrode at or adjacent the source zone through generation of hot charge carriers, characterized in that: said means comprise a thickened portion of the gate dielectric adjoining the source zone, while the pn-junction of the source zone intersects the surface of the semiconductor body below the thickened portion, the source zone and the floating gate electrode, seen at the surface, have edges which coincide at least substantially, and the gate dielectric at the area where the pn-junction of the drain zone intersects the surface is thinner than the gate dielectric at the area of the thickened portion, said memory elements being arranged in a system of rows and columns in a common semiconductor body.

Claim 9

A semiconductor device as claimed in claim 1, characterized in that the gate dielectric and the floating gate electrode extend to above the drain zone, while the gate dielectric has a second thickened portion which is situated above the drain zone and, seen at the surface, is at a distance from the channel.

Claim 10

A semiconductor device with a memory element, comprising: (a) a semiconductor body having a surface; and (b) a field effect transistor comprising the memory element, said field effect transistor including (i) a source zone and a drain zone, each forming a pn-junction with a surrounding portion of the semiconductor body, (ii) a channel region of the semiconductor body between the source zone and the drain zone, (iii) a control electrode, and a floating gate electrode situated between the control electrode and the channel region, said floating gate electrode having a first lateral edge adjacent said source zone and a second lateral edge adjacent said drain zone, and (iv) a gate dielectric extending at said surface of said semiconductor body and separating said floating gate electrode from said semiconductor body, said gate dielectric including a narrow portion and first and second thickened portions, said thickened portions being thicker than said narrow portion and merging into said narrow portion, said narrow portion being located between said lateral edges of said floating gate electrode, each thickened portion extending outwardly from said narrowed portion past a respective said lateral edge of said floating gate electrode and contiguous with a respective one of said source zone and said drain zone, said pn-junction of the source zone terminating at said surface at a lateral location at least substantially coinciding with said first lateral edge of said floating gate electrode, and said pn-junction of said drain zone terminating at said surface at a lateral location between said first and second lateral edges of said floating gate electrode where said gate dielectric is narrower than said gate dielectric location where said pn-junction of said source zone terminates at said surface; said field effect transistor having an electric field strength at said source zone which, as the voltage applied to said control electrode increases, increases at said source zone and decreases at said drain zone and accelerates hot charge carriers generated in said channel from said source zone to said floating gate electrode.

Claim 11

A semiconductor device with a memory element, comprising: (a) a semiconductor body having a surface; and (b) a field effect transistor comprising the memory element, said field effect transistor including (i) a source zone and a drain zone, each forming a pn-junction with a surrounding portion of the semiconductor body, (ii) a channel region of the semiconductor body between the source zone and the drain zone, (iii) a control electrode, and a floating gate electrode situated between the control electrode and the channel region, said floating gate electrode having a first lateral edge adjacent said source zone and a second lateral edge adjacent said drain zone, and (iv) a gate dielectric extending at said surface of said semiconductor body and separating said floating gate electrode from said semiconductor body, said gate dielectric including a narrow portion and first and second thickened portions, said thickened portions being thicker than said narrow portion and merging into said narrow portion, said narrow portion being located between said lateral edges of said floating gate electrode, each thickened portion extending outwardly from said narrowed portion past a respective said lateral edge of said floating gate electrode and contiguous with a respective one of said source zone and said drain zone, said pn-junction of the source zone terminating at said surface at a lateral location at least substantially coinciding with said first lateral edge of said floating gate electrode, and said pn-junction of said drain zone terminating at said surface at a lateral location between said first and second lateral edges of said floating gate electrode where said gate dielectric is narrower than said gate dielectric location where said pn-junction of said source zone terminates at said surface; said field effect transistor having an electric field strength at said source zone which, as the voltage applied to said control electrode increases, increases at said source zone and decreases at said drain zone and accelerates hot charge carriers generated in said channel from said source zone to said floating gate electrode.

Claim 12

A semiconductor device as claimed in claim 8, characterized in that the semiconductor body is made of silicon, the dielectric layer of silicon oxide, and the floating gate electrode of silicon, while the thickened portion of the gate dielectric is formed by an oxide layer which is obtained at least partly through thermal oxidation of silicon material at the area of the source zone.

Claim 13

A semiconductor device with a memory element, comprising: (a) a semiconductor body having a surface; and (b) a field effect transistor comprising the memory element, said field effect transistor including (i) a source zone and a drain zone, each forming a pn-junction with a surrounding portion of the semiconductor body, (ii) a channel region of the semiconductor body between the source zone and the drain zone, (iii) a control electrode, and a floating gate electrode situated between the control electrode and the channel region, said floating gate electrode having a first lateral edge adjacent said source zone and a second lateral edge adjacent said drain zone, and (iv) a gate dielectric extending at said surface of said semiconductor body and separating said gate electrode from said semiconductor body, said gate dielectric including a narrow portion and a thickened portion, said thickened portion being thicker than said narrow portion and including a portion of continuously reducing thickness merging into said narrow portion, said narrow portion being located between said lateral edges of said floating gate electrode, and said thickened portion extending outwardly from said narrowed portion past said first lateral edge of said gate electrode and contiguous with said source zone, said pn-junction of the source zone terminating at said surface at a lateral location at least substantially coinciding with said floating first lateral edge of said floating gate electrode, and said pn-junction of said drain zone terminating at said surface at a lateral location between said first and second lateral edges of said gate electrode at a location where said gate dielectric is narrower than at said gate dielectric location where said pn-junction of said source zone terminates at said surface, and said field effect transistor having an electric field strength at said source zone which, as the voltage applied to said control electrode increases, increases at said source zone and decreases at said drain zone, accelerating hot charge carriers generated in said channel between said source zone and said drain zone to said floating gate electrode from said source zone.

Claim 14

A semiconductor device with a memory element, comprising: (a) a semiconductor body having a surface; and (b) a field effect transistor comprising the memory element, said field effect transistor including (i) a source zone and a drain zone, each forming a pn-junction with a surrounding portion of the semiconductor body, (ii) a channel region of the semiconductor body between the source zone and the drain zone, (iii) a control electrode, and a floating gate electrode situated between the control electrode and the channel region, said floating gate electrode having a first lateral edge adjacent said source zone and a second lateral edge adjacent said drain zone, and (iv) a gate dielectric extending at said surface of said semiconductor body and separating said gate electrode from said semiconductor body, said gate dielectric including a narrow portion and a thickened portion, said thickened portion being thicker than said narrow portion and including a portion of continuously reducing thickness merging into said narrow portion, said narrow portion being located between said lateral edges of said floating gate electrode, and said thickened portion extending outwardly from said narrowed portion past said first lateral edge of said gate electrode and contiguous with said source zone, said pn-junction of the source zone terminating at said surface at a lateral location at least substantially coinciding with said floating first lateral edge of said floating gate electrode, and said pn-junction of said drain zone terminating at said surface at a lateral location between said first and second lateral edges of said gate electrode at a location where said gate dielectric is narrower than at said gate dielectric location where said pn-junction of said source zone terminates at said surface, and said field effect transistor having an electric field strength at said source zone which, as the voltage applied to said control electrode increases, increases at said source zone and decreases at said drain zone, accelerating hot charge carriers generated in said channel between said source zone and said drain zone to said floating gate electrode from said source zone.

Claim 15

A semiconductor device as claimed in claim 10, characterized in that the semiconductor body is made of silicon, the dielectric layer of silicon oxide, and the floating gate electrode of silicon, while the thickened portion of the gate dielectric is formed by an oxide layer which is obtained at least partly through thermal oxidation of silicon material at the area of the source zone.