US4577295A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Hybrid E2 cell and related array
Assignee: Intel Corp
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Filing: 1983-05-31
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Granted: 1986-03-18
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Expires: 2003-05-31
Abstract
Abstract An improved MOS E2 cell is described which includes a floating gate and a thin oxide region. Charge injected into the substrate is used to program the floating gate by hot electron injection through the tunnel oxide region. Erasing is accomplished by tunneling through the thin oxide region. With this arrangement, the capacitance coupling between the floating gate and control gate is greatly reduced, allowing the cell to be substantially smaller. Several novel inhibit modes permit the fabrication of an array without using a selection device for each of the cells.
Inventors
- 👤 Boaz Eitan
- 👤 Avi Kolodny
- 👤 Daniel Amrany
- 👤 James McCreary
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 13:30
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/681; H10D30/684; G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0408; G11C16/0416; G11C16/0433
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
218 words
An MOS integrated circuit, electrically programmable and electrically erasable memory cell arrangement formed on a substrate comprising: a memory cell including; (i) a pair of spaced-apart regions disposed in said substrate; (ii) a floating gate disposed at least between said spaced-apart regions, said floating gate being insulated from said substrate by a first insulative layer and a portion of said floating gate being insulated from said substrate by a second insulative layer through which charge is tunnelled from said floating gate to said substrate, said second insulative layer being thinner than said first insulative layer; (iii) a control gate disposed at least between said spaced-apart regions, said control gate being disposed above and insulated from said floating gate; injection means for injecting charge into said substrate during the programming of said cell; and electrical means coupled to said spaced-apart regions, control gate and injection means for programming said cell such that said injected charge is transferred from said substrate through said first insulative layer onto said floating gate and for erasing said cell such that charge from said floating gate is tunnelled through said second insulative layer into said substrate, whereby the area of said substrate required for said cell may be reduced since the capacitive coupling between said floating gate and said control gate may be reduced.
Claim 2
Dependent Claim
218 words
An MOS integrated circuit, electrically programmable and electrically erasable memory cell arrangement formed on a substrate comprising: a memory cell including; (i) a pair of spaced-apart regions disposed in said substrate; (ii) a floating gate disposed at least between said spaced-apart regions, said floating gate being insulated from said substrate by a first insulative layer and a portion of said floating gate being insulated from said substrate by a second insulative layer through which charge is tunnelled from said floating gate to said substrate, said second insulative layer being thinner than said first insulative layer; (iii) a control gate disposed at least between said spaced-apart regions, said control gate being disposed above and insulated from said floating gate; injection means for injecting charge into said substrate during the programming of said cell; and electrical means coupled to said spaced-apart regions, control gate and injection means for programming said cell such that said injected charge is transferred from said substrate through said first insulative layer onto said floating gate and for erasing said cell such that charge from said floating gate is tunnelled through said second insulative layer into said substrate, whereby the area of said substrate required for said cell may be reduced since the capacitive coupling between said floating gate and said control gate may be reduced.
Claim 3
Dependent Claim
21 words
The memory cell arrangement defined by claim 1 wherein a plurality of said memory cell share one of said injection means.
Claim 4
Dependent Claim
19 words
The memory cell arrangement defined by claim 2 wherein said floating gate and said control gate are polysilicon gates.
Claim 5
Dependent Claim
30 words
The memory cell arrangement defined by claim 3 wherein said second insulative layer is disposed above and ion implanted substrate region which is contiguous with one of said spaced-apart regions.
Claim 6
Dependent Claim
17 words
The memory cell arrangement defined by claim 4 wherein said injection means comprises a doped substrate region.
Claim 7
Dependent Claim
69 words
The memory cell arrangement defined by claim 1 or 5 wherein a plurality of memory cells are disposed in a memory array with one of said spaced-apart regions for each of said memory cells being coupled to a transistor, the gates of said transistors forming select lines in said array, and wherein said other of said spaced-apart regions for each of said memory cells is coupled to ground lines.
Claim 8
Dependent Claim
79 words
The memory cell arrangement defined by claim 1 or 5 wherein a plurality of said memory cells are disposed in a memory array with one of said spaced-apart regions for each of said memory cells being coupled to a bit line in said array and the other of said spaced-apart regions for each of said memory cells being coupled to another line in said array with said control gates of said memory cells forming select lines in said array.
Claim 9
Dependent Claim
150 words
In an electrically programmable and electrically erasable MOS memory array formed on a substrate which includes a plurality of memory cells each of which has a pair of spaced-apart regions, a floating gate and a control gate where a portion of said floating gates are insulated from said substrate by a thin insulative region through which charge is tunnelled, and where the remainder of said floating gate is insulated from said substrate by a thicker insulative layer, an improvement comprising: injection means for injecting minority carriers into said substrate; electrical means coupled to said spaced-apart regions, control gates and injection means for transferring injected charge from said substrate to said floating gate through said thicker insulative layer to program said cells and for tunnelling charge from said floating gate through said thin insulative layer into said substrate to erase said cells; whereby an improved erasable MOS memory array is realized.
Claim 10
Dependent Claim
150 words
In an electrically programmable and electrically erasable MOS memory array formed on a substrate which includes a plurality of memory cells each of which has a pair of spaced-apart regions, a floating gate and a control gate where a portion of said floating gates are insulated from said substrate by a thin insulative region through which charge is tunnelled, and where the remainder of said floating gate is insulated from said substrate by a thicker insulative layer, an improvement comprising: injection means for injecting minority carriers into said substrate; electrical means coupled to said spaced-apart regions, control gates and injection means for transferring injected charge from said substrate to said floating gate through said thicker insulative layer to program said cells and for tunnelling charge from said floating gate through said thin insulative layer into said substrate to erase said cells; whereby an improved erasable MOS memory array is realized.
Claim 11
Dependent Claim
13 words
The array defined by claim 8 wherein said substrate is a p-type silicon.
Claim 12
Dependent Claim
14 words
The array defined by claim 9 wherein said insulative layers comprise silicon dioxide layers.
Claim 13
Dependent Claim
19 words
The array defined by claim 8 wherein one of said injection means is shared by a plurality of cells.
Claim 14
Dependent Claim
17 words
The array defined by claim 11 wherein each of said injection means comprises a doped substrate region.
References Cited (Backward Citations)
US4435790A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-03-17 | 1989-09-16 | 1990-03-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-03-17 | 1993-09-16 | 1994-03-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-03-17 | 1997-09-16 | 1998-03-18 | $7700.00 | Window Closed / Lapsed |